Study Of Scan Based Dft Techniques For Short Test Time And Low Test Power

Integrated circuits(ICs) are not immune from various physical defects, so testing is an essential method to guarantee the product yield. However, the design complexity of IC is increasing rapidly and this brings forth a great challenge for IC testing. Design-for-testability(Df T) makes it easier to develop and apply manufacturing tests for the product design by adding specific design structure into circuits. Scan design is the most popular technique among current different Df T techniques. However, scan design will introduce severe problems for circuit under test(CUT) during test, such as high test power dissipation, long application time and great test data volume.It has been proven that the test power is proportional to the number of overall transitions during test. Scan cell ordering is an effective scan path organization method to reduce the number of transitions, hence the test power. In this work, a new scan cell ordering method is proposed based on evaluating exact number of transitions introduced by two connected scan cells. Two complementary scan cell connection styles are introduced to further reduce the scan transitions. The experimental results show that when compared with the original scan chains, the scan chains created by the proposed method can reduce transitions by 43.7% on average. The method also reduces transitions by 6.5% on average compared with other existing scan cell ordering methods with regard to test power optimization.One drawback of scan chain ordering is that it results in too long connection and routing congestion. To solve this problem, a new scan design method is proposed to optimize test power under the routing constraint. K-means clustering algorithm is first used to divide the scan cells into K groups based on their distribution property prior to the ordering. Under routing constraint, some flexible scan cells which can be moved to the neighbor groups are identified and regrouped to reduce the transitions, hence the test power. Scan cells are finally ordered based on the proposed scan cell ordering method. The experimental results show that the scan designs implemented by our method can save 18.9% test power compared with the original scan design. In addition, when compared with the designs implemented by other optimization methods, the proposed method can reduce more than 10.2% transitions while satisfying routing constraint.High test data volume and long test time are other two problems introduced by scan based design. Test data compression technique and broadcast-based decompressor architecture have been combined together to solve these problems. Among which, it is key to improve the percentage of broadcastable test patterns(broadcast ratio). A new decompressor architecture with bidirectional shift register is proposed. It enables a new broadcasting mode, which can achieve a higher broadcast ratio and cost less test time. A heuristic method is proposed to reorder the scan cells in each sub parallel chain to improve the broadcast ratio so as to reduce the test data and test time. The experimental results show that compared with other broadcast-based scan architecture, scan designs by our method can reduce the test data by 22.8% and shorten the test application time by 19.5% on average while achieving same fault coverage.