Research On Low-Power Test In VLSI Scan Test

With the development of the VLSI manufacture technology, the higher and higher degree of integration has made the test power consumption as one of the main concerns of VLSI designs and tests. Generally speaking, VLSI consumes much more power in test than in normal motion, which can give rise to reliability to bate, even in some cases cause circuit damage. The importance of low-power test of VLSI is increased in today's VLSI design and manufactere.Scan structures used in VLSI tests give a very good solution for increasing the controllability and observability of internal nodes of the circuit. They have also successfully been used in the prevalent approaches of Design for Testability (DFT). Therefore, the study on low-power-methods in scan tests is of important significance for borth theory and utinity.The dissertation discusses some problems, such as static and dynamic power consume, test vectors, scan chains and scan cells and so on. Some methods for reducing test power in scan test are proposed and experimentally verified. The main work and innovation are depicted as follows:(1) A novel approach for parallel core wrapper design (pCWD) is presented to reduce test power by shortening wrapper scan chains and adjusting test patterns. Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match between TAM and internal scan chains. However, existing serial connection of internal scan chains incurs power and time waste. Study shows that the distribution and high density of don't care bits (Xs) in test patterns make scan slices overlapping and partial overlapping possible. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. The experiment results on d695 of ITC2002 show that the shift time and test power have been decreased by 1.5 and 15 times, respectively.(2) Aiming at the problem that the static power dissipation caused by leakage current in CMOS circuits during test has occupied a significant part in the total dissipation, we propose a method for static test power optimization, which can minimize the static dissipation by using leakage current simulator and assigning proper values for Xs and searching for the minimum leakage vector (MLV) on the bases of analyzing transistor stacking effect. The experiment results indicate that the proposed method can effectivelly reduce leakage current of combinational and sequential circuits during test while maintaining high fault coverage.(3) In the CMOS technology of nowdays, dynamic power consumption is the dominant part of test power consumption, thus how to decrease the dynamic consumption of test is a very important problem. To this end, we propose a method SCANGIN for reducing the dynamic consumption during the shift stage of scan, which can avoid many unnecessary reversals on a scan chains. The experiment results on ISCAS'89 show that the proposed approach can reduce average power dissipation in scan test by 88.9% with just a little area overhead. (4) We propose a method using the low-power scan structure named PowerCut to minimize power consumption in scan test, which is based on a scan chain modification technique. In this method, an obstructive logic circuit is inserted into the scan chain to reduce the dynamic power and a control unit is used to decrease the leakage power in the shift stage and the genetic algorithm is used to get proper values of control signals. Some experiments are made and the results indicated that this method can effectively reduce power consumption in scan test and maintain the test fault coverage. When the average fanout number is more than 1.5, PowerCut has the least area among the existing gating techniques.