The Research Of SOC Test Method Based On RAS Architecture

The rapid progress in micro-electronic technology promotes the advent of System-on-a-Chip (SOC), which brings integrate circuit (IC) into a new period of development. The design of SOC mainly adopts the technique of reusable intellectual-property (IP) cores, so it can accelerate the process of development and improve the system performance. However, with the development of the VLSI manufacture technology, the higher and higher degree of integration in a circuit and the increase number of IP cores integrated, and its function becoming more complex, test data volume grows quickly, and test access is also more difficult. All these cases pose the more challenges for SOC test.Scan structures used in VLSI tests give a very good solution for increasing the controllability and observability of internal nodes of the circuit. They have successfully been used in the prevalent approaches of Design for Testability (DFT).But along with the manifold of test data volume, the tradition serial scan's characteristic made the scan structures doesn't coincident with the need of today's test. The Random Access Scan method can deal with three test problem: test data volume, test power dissipation and test application time. This dissertation makes research in the architecture of RAS , the RAS scan cell and test data compression , test power dissipation and test application time based on the RAS.The dissertation analyses the RAS's basic architecture, and improve the two-dimension address structure accord the RAS characteristic, and at the same time, make use of the reverse output of the flip-flop to reduce the flip-flop's overhead further. Compare with the tradition serial scan method, the RAS method's test power dissipation can be ignored, with the great reduction in test data volume and test application time.Meanwhile, the dissertation make use of the compatibility of the test vector to group the scan cell ,and further optimize the new test set aimed at the test power dissipation. Experimental on benchmark circuits have shown on average77.53% reduction in test data volume, and compare with other test method based on RAS, our method excelled other method much at test data compression ratio and test application time.