Research On Test Data Coding Compression Technology Of VLSI

With the circuit scale,integration,structural complexity and operating frequency rising,Semiconductor technology got into the deep submicron system and nano era.Complex public core/multi-core chip system continues to emerge,and high-speed testing needs to take up more test bandwidth and more test application time.How to effectively test the circuit without compromising the quality of the test set,and how to reduce the test application time,are very important.In this paper,three kinds of significant test data coding algorithms are proposed,which can compress the test data effectively,the decoder structure is simple and easy to implement.The main work is as follows:(1)Proposed a test data compression method for System-on-chip using flexible runs-aware PRL coding,the coding algorithm is easy to use.The inner code iteratively encodes 2~n compatible or inverse-compatible sub-segments within a single segment.The external coding codes multiple compatible or inverse-compatible segments,which break the limit in 2~n-PRL.The decoder architecture is simple and easy to implement.The benchmark circuit experimental results show that the flexible run-length coding method achieves higher compression ratios and shorter test application times.(2)Proposed a hybrid test data compression method for full scan testing using multi-group clock gating.Due to the system-on-a-chip scanning test,power consumption and test application time is becoming two serious problems.A large number of scanning units cause excessive switching activity during a scan shift operation.This method combines the internal block merging and the external alternating counting rules,the corresponding decoder is designed,and its hardware architecture is simple and easy to implement.The further application of multiple-clock-gated full scan test schemes greatly reduces the switching rate of the internal combinational logic and prevents the cumulative conversion caused by the shift operation of the scanning unit.The experimental results show that the method has a good performance with an average compression ratio of 72.57%.In addition,the full-scan test scheme based on clock gating facilitates the reduction in synchronization overhead and scan test power.(3)An adaptive test data coding method using mismatch address indexing and merging group counting for system-on-chip testing is proposed.In order to achieve a high compression ratio,the scheme is used to compress compatible,inverse-compatible and mismatch patterns into short codewords.In addition,it is adaptively selected whether or not compress the mismatch patterns during the encoding process.In order to correctly decode the mismatch pattern,a mismatch address index scheme is introduced.Also,the corresponding decoder design architecture is simple and easy to implement.The verification experiment on the ISCAS benchmark shows that the proposed coding method achieves high compression ratio,low hardware overhead and less test application time.