| To ensure the quality of integrated circuits (IC) products, testing is a very important procedure. However, as complexity and integration of the circuit under test (CUT) are increasing, testing becomes very difficult. The test cost is very high. Therefore, how to solve the test problem of excessively high costs to implement efficient testing of the IC become extremely important. A scan test scheme based on scan chain disabling technique has been proposed, which can effectively reduce test power. However, its test application time is long.To overcome the shortage, this thesis proposes a method for test application time reduction based on TSP problem. The proposed method uses the compatibility between test vectors to reduce test application time. Its implementation process as follows. Firstly, the test vectors to be applying to the CUT are regarded as nodes. Then, scan shifting all of these test vectors is as traversing all these nodes. These nodes construct a complete graph through the distance between the nodes, and then the problem of minimum test application time will be regarded as the problem of minimum distance which traversed all nodes of the graph. The problem is equivalent to non-symmetric TSP problem, which can be solved using some heuristic algorithm. The experimental results show that, the method can effectively reduce test application time without additional hardware costs.This thesis also improves the scan chain disabling scheme by inserting controllable LFSR to minimize test application time and test data storage. The test vectors of some sub-scan chains generate by controllable LFSR when these chains only need to update test vector and do not need to shift out test responses. Controllable LFSR can adjust test vector sequence generated by original LFSR through control codes which stored in the ATE or ROM. The proposed method can reduce test application time and test storage using a simple structure that just added a small amount of hardware. |
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