Research On Application Time Minimization Techniques For Testing System On Chip

Developing flow of very large scale integrated (VLSI) circuits is divided into four main steps: designing, manufacturing, testing and packaging. Testing is an important process for industrial production of VLSI chips, the goal of which is to detect circuit faults caused by manufacturing process. The methods of testing VLSI circuits mainly include ATE-based external test, build-in self-test (BIST) and test resource partition (TRP) based optimization test. The advancement of VLSI design and manufacturing techniques promotes the repid development of system on chip (SoC). However, testing SoC is very costly due to the increase in test data volume and the difficulty with accessing the embedded cores, and SoC testing is a great chanllage. Reduction of test application time (TAT) can decrease SoC test cost and test power dissipation. Optimizing TRP is a main technique for minimizing SoC test application time, which includes test data compression (TDC), design for testability (DFT) and test scheduling. The prior work and achievement related to these techniques are summarized. Aimming at minimizing SoC test application time, this dissertation explores new solutions to compressing SoC test data and optimizing core/SoC test access and application architecture.Balance partition of core wrapper scan chains can decrease SoC test application time and ATE memory requirement for testing SoC. This dissertation presents a solution to designing balanced wrapper scan chains for hard cores under given width of test access mechanism (TAM), in which a so-called best interchange decreasing (BID) algorithm is proposed. Starting with a primary wrapper scan chains partition created by using the known LPT algorithm, the proposed technique optimizes the current configuration through iteratively using the BID algorithm, in which a pair of wrapper chains with the maximum difference in length is selected and the optimal two scan cells are located and then interchanged between the two wrapper scan chains. The proposed technique is applied to the typical cores of ITC'02 SoC benchmarks. The experimental results show that compared to the previous methods, the proposed technique can create more balanced wrapper scan chains, with good convergence and moderate computational time.Generally speaking, a pre-computed core test set contains a large number of don't care bits (x bits or x's) that can be exploited to improve test data compression. This dissertation addresses test data compression, aiming at high compression rate and low decoding overhead. A novel dynamic x-propagation and backtrack filling strategy is presented to extend the pattern run-length (PRL) coding approach (EPRL). The proposed technique propagates the remaining x's of the reference pattern that stops running into the next reference pattern in such a way that the reference pattern is XOR-ed with the pattern to be encoded, increasing the probability of the new reference pattern being coding-compatible with the next patterns to be encoded. On the other hand, the x-propagation strategy can be validated by filling some x's of the already-encoded patterns in backtrack way. How the new x-ploiting strategy is applied to test data compression is demonstrated. Experimental results for test sets of six large ISCAS89 benchmarks show that compared to the TDC techniques presented recently, our scheme can improve compression effectively and require a simple on-chip decoder.Based on the work above, a core-unified SoC test data compression and application scheme is also proposed in this dissertation, in which more than one core test sets of SoC are unified into a single data stream that is then compressed by the EPRL encoding technique presented in the previous part of this dissertation, making full use of the x-propagation strategy. A kind of reconfigurable core-unified scan test architecture is presented to apply the test data of different cores in parallel way, which cooperates with the core-unified test data compression/decompression. The new test scheme is applied to an academic SoC consisting of six large ISCAS'89 circuits, and also to the typical modules of ITC'02 SoC benchmarks. Experimental results show that compared with the existing techniques in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve the efficience of test data compression/decompression, but also decrease SoC test application time through reducing the redundant shift and capture cycles during scan testing. The hardware overhead required for reconfiguration is very low due to clustering of the scan cells of each core in union scan chains.