Research On Test Optimization For Multicore SOC Based On Dynamic Voltage Scaling And Multiple Voltage Island

As a popular kind of system chip,multicore SOC based on DVS and MVI with the advantages of low power consumption and high performance,has gotten wide attention in the field of aviation,aerospace and other electronics fields.However,with the rapid development of IC manufacturing technongy,test technology for multicore SOC based on DVS and MVI faces major challenges: On the one hand,it will take a lot of time to ensure fault-free operation of the large scale and even very large scale SOC.On the other hand,additional multiple voltage tests and state retention tests must be applied to ensure normal operation of DVS and MVI,which leads to a rapid increase in testing time and cost.Therefore,it is very meaningful to study the optimization technonlgy of testing time for IP cores and system.To the optimization problem for the test time of multicore SOC based on DVS and MVI,we launched three part of research from scan chain wrapper design,IP core wrapper structure design and test scheduling algorithm respectively to reduce the test application time:(1)In order to solve the problem of IP core scan chain balance wrapper,we proposes the scan chain balance algorithm based on integer-float portions separation and recombination(IFSR),the main ides is that we selects a datum blocks as the basic units of ruler and measures the length of scan chain to get integer-float portions,then determines the result of the IP core wrapper through approximate wrapper and recombination.Experimental results of the ITC'02 So C Benchmark show that compared with BFD,MVAL,TAD(ADJ)algorithm,IFSR algorithm can acquire more balance wrapper result,and reduce the test application time of IP core effectively.(2)In order to solve the problem of multi-voltage retesting by single test stimuli,we proposes a modify wrapper structure,named IP cores resource multiplexing(IPRM).The IPRM core wrappers can enable to isolate d core wrapper resource again to act as virtual test source and sink by storing test data for embedded cores under test,which implements the line operation for multi-voltage repeated test tasks and improves the efficiency of TAM effectively.Finally,a ma th formulation with IPRM wrapper is proposed to improve multi-site test,and applied to ITC'02 SOC Benchmark.Experimental results show compared with IEEE1500,IPRM core wrapper can reduce the test application time by 10–50%.(3)In order to solve the optimaization problems of test scheduling further,we establish a mathematical model to the line test and proposes a differential evolution algorithm with multiangle searching strategy-based rotating crossover operator(JADE-Ma S).Finally,the algorithm is applied to ITC'02 SOC Benchmark.Experimental results show compared with GA,PSO algorithm,JADE-Ma S algorithm can reduce the test application time effectively,the optimized proportion by IFSR methods reached 66.67%.