Core-test Technology And Application In SOC Design

With the development of semiconductor and improvement of design level,IC design industry has been entered the SOC (system-on-chip) era. A great number of transistors were intergrated into single chip which can complete more complex functions. Because of the increasingly demands of the market and shorter cycle of chip design, SOC was made of lots of standards IP cores that has gradually become the main method. Therefore, the SOC has two notable features which is large-scale and is made of a large number of embedded IP cores. The manufacturing fault will also increaced with a large-scale chip,so that have higher requirements for SOC test which including more precise timing control and longer testing time, that would result in more testing costs. The SOC chip uses large number of IP cores, because of limitting the use, license, protection of IP cores that will meet many challenges, SOC test becomes more and more difficult than ever because different multi IP cores will be intergrated into a system. So the study of SOC test is of great importance in the theory research and the practical application.Based on studying IEEEstd1500 standard in detail,this paper presents a test IP cores reuse system which includes hardware proportion and software proprotion for embedded core test reuse. The hardware proportion includes test wrapper design and TAP design which will generate signals needed by the IEEEstd1500 standard .The sofeware proportion includes the test vectors generation module, test information extraction strategy module by Std1500TAM test strategy. In addition, FPGA test platform was application of the test strategy. Simulation model was designed to test and to generally accepted benchmark on the ITC'02 test circuit for testing.Simulation and practical test results show that the methodology is feasible.The performance of the test system meets with requirements of SOC test.The test system illustrated in the dissertation has a prospective future in the applications.