Research And Implementation Of IP Core Test Access And Low-Power Testing Methodology On Scan Chains

With the continuous advances in semiconductor technology, IC follows Moore's Law, and therefore the scale and complexity of circuit have a trend of increasing. Faced with these challenges in circuit design, the design methodology of So C emerges. So C reuses IP cores provided by the third parties, which can greatly reduce the complexity of circuit design, improve reliability, shorten design time, thus becoming the mainstream design methodology. So C Based on reuse of IP cores brings convenience in the circuit design, at the same time, adds new challenges and problems in design for test.IP cores embedded systems continue to increase, as well as the depth of the IP cores embedded system, which seriously influences the transparency of the IP core test access, reducing IP core test coverage; when IC tested, the correlation of test vectors is very small in order sensitizing circuit fault as much as possible in the shortest time, resulting in a higher number flip of circuits in a short time and causing power consumption in test mode higher than the normal mode. Reducing the power consumption in IP core testing is an issue to be urgently addressed.This paper starts from the domestic and international research hotspot, carried out research in two sides: IP core test access and low-power testing on Scan Chains.The main work and innovations are as follows:1?The IP core test standard —IEEE Std 1500 is studied and analyzed in the paper. For the shortcoming of IEEE Std 1500 Standard in engineering applications, we propose a simplifying WBR composition. The composition can be targeted to improve IP core test observability and controllability, at the same time, reduce hardware overhead, compared with the typical WBR composition.2?The paper verifies the effectiveness of the program through a simplifying control method. Experimental result shows that the simplifying WBR can effectively improve the IP core test coverage by 6.99%—21.78%, but decrease hardware overhead by 50% compared to the typical WBR.3?The generation of dynamic power in IP core scan chain is analyzed in the paper. According to the characteristics of dynamic power, the paper proposes a partial suppression technology in the output of scan chains based on the type of scan unit. On this basis, the paper proposes a heuristic filtering strategy. Under the area constraints of a chip, the filtering strategy provides a local optimum solution. It can reduce peak power and average power while not increasing hardware overhead compared to the full suppression technology in the output of scan chains.4?Built the experimental environment in which the partial suppression technology in the output of scan chains is carried out based on the not-custom standard library and verify the effectiveness of the techniques. The experimental result shows that peak power reduces by 8.04%~18.09% under the area constraints of a chip, as well as average power by 13.33%~14.70%.