| Core-based designs pose a significant test challenge. For intellectual property cores, no information may be given about the internal logic of the core (i.e. it is a black box). In that case, the traditional test generation process such as ATPG (automatic test pattern generation) and fault simulation cannot be performed. Instead, the core vendor specifies the set of test vectors that must be applied to the core to guarantee certain fault coverage. The problem is how to apply the specified test vectors to the core and how to test the logic surrounding the core.; In deterministic testing, where an external tester is used to apply the test vectors, the user-defined logic (UDL) surrounding the core may restrict the set of test vectors that can be applied to the core. Some of the specified core test vectors may not be contained in the output space of the UDL that drives the core and hence cannot be justified at the core inputs. Two novel approaches to provide functional access to the core are presented. One approach is to design a partial isolation ring as opposed to a full isolation ring by justifying some of its bits through UDL. Another one involves synthesizing the UDL in such a way that its output space contains the specified core test vectors. An approach for synthesizing output compaction circuitry that reduces both the test overhead and test time needed to observe the test response in a core-based design is also presented.; In built-in self-test (BIST), on-chip hardware is used to test the circuit. In the second part of the dissertation, synthesis techniques that support a self-test methodology for testing core-based designs are presented. Techniques for synthesizing test pattern generators that provide patterns for the entire system and UDL are described. An algorithm for synthesizing UDL such that it is fully testable by the test pattern generators are presented. The end result is self-test functionality in the entire core-based design which allows at-speed testing with low-cost test equipment. |
