Research Of Scan Chain Inserting And Test Wrapper Installing In IP Core Design For Testability

With the increasing number of integrated transistors on SoC, the chip faults causedby the manufacturing process are more, so it is necessary to test the chip for guaranteeingthe quality of products. However, when IP core is embedded into SoC, The input andoutput ports will lose the observability and testability, so DFT(Design For Testability) isproposed. After the further study of DFT and DFT methods, this paper designs a softwarethat can complete the scan chain inserting and the wrapper installing.At first, the paper studies the meaning and methods of DFT, and the full scanningmethod is adopted in this paper. Then IP core test wrapper is made based on IEEE1500standard. The paper writes the core modules program of software that can complete DFTof IP core automatically by Perl language. The core modules include three functionmodules, they are EDIF netlist analysis module, internal scan chain design module andtest wrapper installing module. Then DFT of IP core will be completed by these threemodules. The paper designs the good interpersonal interaction interface by C++language,the input files of each module and the users’ information will be input by this software,Finally, IP core DFT will be completed automatically by running these three modules.To test the software in this paper, the installing effect of testability structure can betested by connecting Quartus II and ModelSim Software. The result shows that IP corecan complete the scan chain inserting, and the running state of each test instruction isconsistent with the theoretical analysis. The software in this paper can quickly andaccurately complete IP core DFT, so it has certain practical value.