Research And Analysis Of Design For Testability Based On PCIE IP Core

With continuous development of integrated circuit industry, chip size is larger and larger and operating frequency is faster and faster, which bring great challenges for chip test. How to test chips efficiently with reasonable cost and time has become research focus in the integrated circuit area. Fortunately, Design For Testability(DFT) techniques overcomes the difficulties and find an effective solution for chip test. DFT has become a vital part in current chip design flow.Deep discussion and research in the principles and concepts of DFT techniques are given. And the fault model and some kinds of popular testing methods are introduced. In addition, based on a real chip PCIE which is a part of large-scale DSP communication processor chip HR2, a complete set of DFT plan which includes scan test, MBIST, and at-speed scan test is made according to its structure and characteristics. And these test methods and auto test pattern generation(ATPG) are implemented to verify the DFT design flow.Test coverage, simulation time, test time, and test power consumption are researched deeply and optimized according to PCIE test demands. Scan test coverage of PCIE is increased to 98.16% by solving the problems that register ports can’t control and shadow logic around memory can’t test. Scan simulation time and test time of PCIE is reduced to 0.15 hour and 196.780 ms respectively by implementing scan compression, simplified test patterns, and parallel simulation techniques. Scan test power consumption of PCIE is decreased to 99.4m W by optimizing indifferent bits of test patterns and adding combined logic gating. Peak scan test power consumption of HR2 is decreased by 86% by adding IEEE P1500 structure. Besides, PCIE physical design is completed based on TSMC 45 nm technology and layout area is 3.866 mm ×1.945 mm.Finally, based on the analysis of PCIE, one complete chip design flow with DFT and especially each step of DFT flow are summarized.