Research On SoC Test Optimization And Application Technology

The rapid improvements in micro-electronic technology promote the advent of System-on-a-Chip (SoC). Although the technique of reusing IP (Intellectual Property) cores could accelerate SoC design process, SoC test encounters great challenges because of the proliferation of the integrated IP cores and their functions being more complex. In order to reduce the SoC test complexity, this dissertation does research in test data compression, test power optimization and test wrapper design, and has proposed many SoC test optimization techqiues.In order to solve the problem of test access, the IEEE 1500 standard is carefully studied. This dissertation describes the design of test wrapper for embedded IP cores and verifies the test wrapper's efficiency under different test instructions through simulating experiments.Research the technique of test data compression. A Variable Prefix Dual-Run-Length (VPDRL) code was proposed, which has two steps: firstly, the don't care bits in test data are filled with 0s or 1s using the dynamic programming algorithm; then according to the novel partition way, the test data was divided as alternate runs of 0's and 1's. Test compression methods for multi-scan chains are also discussed. A test compression method using Unfixed-Based Index (UBI) dictionaries and bitmask is proposed, which uses shorter indexes to represent the slices of higher occurrence frequency. Moreover, we adopt efficient bitmask and max-degree based clique partition algorithm to create as many compatible slices as possible.Research the technique of test power optimization. An improved test wrapper cell is proposed, which inserts only a CMOS transmission gate into the traditional IEEE 1500 wrapper cell. Experiments indicate that this improved wrapper cell not only takes less area overhead and time delay, but also can reduce the dynamic test power consumption during scan shifting. Meanwhile, a test power optimization algorithm based on scan chain reconfiguration and clock congelation is discussed. Simulation experiments on navigation SoC show that this low power scheme could reduce the dynamic power.