Design Of MIPI D-PHY And MIPI C-PHY Interface Chip For High-Speed Video And Image Transmission

MIPI(Mobile Industry Processor Interface)interface protocol,which has been widely used,is the mainstream protocol in the field of video image transmission.At present,most of the middle and high-end mobile displays equipment and cameras use MIPI C-PHY or MIPI D-PHY interface.The demand for processing video images of mobile devices is growing rapidly,so high-speed interfaces require higher performance.The previous MIPI C-PHY and MIPI D-PHY interface chips cannot meet the higher bandwidth demand,so it is necessary to develop MIPI C-PHY and MIPI D-PHY interface chips with better performance and higher transmission rate.MIPI A-PHY chip technology,based on MIPI C-PHY chip and MIPI D-PHY chip technology,has become a research hotspot in the field of automotive electronics,and chips which combine C-PHY and D-PHY protocols are becoming more and more popular.All these require the simultaneous development of higher performance MIPI C-PHY chip and MIPI D-PHY chip.This paper mainly explores the design and completion of the high-speed interface of video image transmission in MIPI D-PHY transmitter chip and MIPI C-PHY receiver chip.So far,most MIPI D-PHY and MIPI C-PHY chip design papers have not systematically delved into the digital part of the chip.This paper makes an in-depth exploration into this digital part and fills the gaps in this aspect.MIPI D-PHY transmitter chip complies with MIPI D-PHY v2.5 protocol version,it supports up to 4data channels and a clock channel for parallel transmission,which uses enable signal switching to control the mode of state transition,and provides the corresponding signal to the analog part according to the state,and the chip,as a whole,uses state machine linkage control.The supportive working states mainly include power-on protection,deskew mode,high-speed transmission,low-speed transmission,and low-speed reception after flipping.MIPI C-PHY receiver chip follows the protocol version of MIPI C-PHY v2.0,which supports four data channels,uses pipeline design method to analyze the received signal of high and low speed,and makes full use of the advantages of embedded clock for sampling,uses the enable command to switch states,and in the meantime the chip supports high-speed reception and low power consumption reception function.The innovation of the chip design arrangement includes:the MIPI D-PHY transmitter chip adopts the state machine linkage control method,uses registers to configure the duration of each state stage to increase compatibility.Power consumption is saved by using low speed clock to configure high speed state duration.The MIPI C-PHY receiver chip applies a pipeline design method,uses an external clock to control the state switch of the enabled state machine.The random clock is directly used as the data acquisition clock.The chip also uses register configuration phase duration and supports automatic synchronization codes and data offset correction within two beats.This paper describes the digital front end design flow of the chip in detail.The design uses Verilog HDL language.MIPI C-PHY chip and MIPI D-PHY chip are mixed digital and analog chips.When the digital simulation is carried out,the chip simulation part is transformed into a digital simulation model for connection.The verification scheme of MIPI D-PHY transmitter chip employs the method of connecting and comparing with the D-PHY receiver chip,which is convenient and quick.The interface signal simulation diagram in line with the protocol is generated in the verification process.The MIPI C-PHY receiver chip is verified by UVM verification platform,and the double comparison method is used to increase the reliability.The detailed function points are listed,and the final code coverage of 98.07%is obtained.TSMC 6 nm standard process library,which has not been used in previous related papers,is used in DC synthesis,and better performance,area and power consumption are achieved.The MIPI D-PHY transmitter chip has a maximum bandwidth of 5.0 Gbps per channel.The integrated area excluding wiring of the digital part of the MIPI D-PHY transmitter chip is 733.17μm~2,and the power consumption is 193.27μW.The MIPI C-PHY receiver chip can achieve a transmission rate of 4.0 Gsps at the fastest speed.The integrated area excluding wiring of the digital part of the MIPI C-PHY receiver chip is 532.47μm~2,and the power consumption is 408.70μW.