Design Of High-speed Transmission Interface For AMOLED Display

With the vigorous development of interactive mobile phone terminal services,traditional display screens have been unable to meet people's requirements for the display quality of smart phones.Throughout the entire industry,the high-end mobile phone market is now developing towards AMOLED screens,and high-end screens require the support of high-performance display driver chips and data transmission interfaces.Based on the latest MIPI DSI-2 and MIPI C-PHY protocols of the MIPI Alliance,this paper studies and designs a high-speed display data transmission interface that combines the D-type physical layer and the C-type physical layer.Compared with the existing display interface based on the D-type physical layer,it can be adapted to a variety of host computer transmission methods,and the transmission interface based on the C-type physical layer can provide a higher transmission rate to support a higher display frame rate and screen resolution.This paper studies the basic architecture of AMOLDE screen and its driver chip,and then studies the overall architecture and related protocols of the high-speed transmission interface MIPI.The general architecture of MIPI interface combining C-type physical layer and D-type physical layer is proposed.The MIPI interface circuit can be divided into four layers according to the function,namely the physical transmission layer and the channel management layer,the bottom protocol layer and the application layer.This paper focuses on the physical transmission layer.This paper introduces the encoding and decoding mechanism in the design of the physical transmission layer,and transmits the data after encoding to improve the transmission rate.In order to solve the problem of internal clock handshake after increasing the transmission rate,on the one hand,this article reduces the recovered clock frequency in order to shake hands with the internal clock.On the other hand,serial-to-parallel conversion is performed on the data,and the data processing bit width of the data channel is increased from 16-bit to 32-bit to reduce the timing conflict of the high-speed clock and the power consumption in the high-speed mode.In addition,the high-speed transmission module and the low-power transmission module are separated to realize the free switching between the low-power mode and the high-speed mode,and to achieve the MIPI high-speed and low-power design goals.The entire design uses Verilog-HDL hardware description language to write RTL-level code,use VCS software for functional simulation,Verdi software for simulation waveform inspection,and n Lint for code inspection and optimization.The process library uses 80nm process.The report obtained by DC synthesis shows that the total area of the interface circuit is 522444?m~2,and the power consumption is 6.3605m W.After the post-simulation test,its single-channel data transmission rate can reach 1.1Gsym/s,that is 2.5Gbps,the overall transmission rate is 1.7 times higher than the existing D-based physical layer interface circuit speed,and the power consumption is controlled within 7m W,And finally completed the optimization and upgrade of the existing interface.