Research And Design Of D-PHY Chip For AM-OLED Display Interface Supporting MIPI Standard

MIPI is a flexible source-synchronous serial interface standard used to connect displays and camera modules on a host or mobile device.It has the advantages of low power consumption,high rate transmission,and strong anti-electromagnetic interference capabilities.The MIPI physical layer directly affects the signal transmission rate and signal quality,and has always been a research hotspot.This paper designs a complete,faster and better performance MIPI physical layer for AM-OLED display driver chip.In the design of high-speed modules,high-speed transmitters using differential signal generators and H-bridge structures are proposed to support synchronous differential high-speed data transmission on the basis of scalable low-voltage signals.The principle and analysis method of eye diagram formation are introduced.A new high-speed receiver circuit has also been proposed.The high-speed receiver uses a differential amplifier to stably receive transmission data with DC variations and AC noise.Based on the requirement of higher speed,the negative feedback of the resistor at the input stage increases the bandwidth and improves the stability of the signal at high speed.In the output stage,a linear amplifier based on NOT gate is used to increase the gain and perform waveform shaping.The traditional bandgap reference circuit is introduced,and the reference source circuit of the high-speed receiver is designed.Completed the layout and post-simulation of the high-speed receiver.In the low-power module,a new type of low-power transmitter is designed,which uses a push-pull driver to control the slew rate and limit the current,which reduces electromagnetic interference and meets the MIPI slew rate requirements under different loads.The low-power receiver proposes a structure which two comparators and SR latches are combined to achieve the hysteresis effect,and has better anti-interference ability.The low-power receiver can filter radio frequency interference and spikes.The difference with the low-power receiver is that the low-power contention detector has a lower VIL and VIH.Therefore,this article uses internal positive feedback to achieve hysteresis.This article uses UMC 80nm CMOS technology under 1.2V power to design all analog modules that meet the MIPI D-PHY specification,including high-speed transmitter(HS-TX),high-speed receiver(HS-RX)and bias circuit,low power transmitter(LP-TX),low power receiver(LP-RX)and low power contention detector(LP-CD).The simulation results of each module meet or exceed the specification requirements.The most critical high-speed receiver circuit at a signal transmission rate of 1.5Gbps,power consumption is 3.5mW,jitter is only 14ps,far less than the standard 42ps.