Research And Design Of Display Driver Interface Based On MIPI DSI-2-2 Protocol

With the rapid development of science and technology,the screen is penetrating into every life scene in various forms,changing the way of human-computer interaction.AMOLED materials have been widely used because of their lighter weight,brighter color,no need to rely on backlight,low energy consumption and good flexibility.The interface protocol developed by MIPI Consortium is widely used in the field of Internet of Things.Currently,most of the AMOLED display driver interfaces use MIPI DSI protocol based on D-PHY structure.With the increasing resolution and refresh rate of the screen,the interface needs to transmit more data per unit time.Due to the influence of chip power consumption and electromagnetic radiation between chips,the C-PHY structure with higher transmission efficiency will be the focus of future research when the transmission rate is limited.It is especially important to develop dual-mode display interface to support C-PHY and D-PHY.By comparing the similarities and differences between C-PHY structure and D-PHY structure,based on the DSI interface circuit of D-PHY structure,a DSI-2 interface circuit based on combined PHY structure is designed by adding CDR circuit and decoding and de-stringing circuit to the original high speed receiver of D-PHY structure.The structure can switch C-PHY and D-PHY modes flexibly without adding pins.By adding delay modules at both ends of the high-speed receiver and CRD circuit,the phase relationship between the recovery clock and the original data can be adjusted to ensure the correctness of data sampling processing during transmission.In the channel management module,the addition of SWAP module can adapt to a variety of FPC board connections,which improves the compatibility of interface circuit.To solve the problem of multi-clock domain caused by multi-channel data input in high-speed transmission in C-PHY mode,the data is converted to system clock domain uniformly in the channel management module.To ensure the aligned output of multi-channel high-speed data,a data synchronization module is added after the conversion of the clock domain is completed.In order to simplify the control logic complexity and increase the area caused by multi-channel input,the output is uniformly converted into a fixed number of channels in the channel management module.A unified state machine is used to control the high-speed receiver and low-power transceiver circuits in the physical layer,which simplifies the complexity of the physical layer control module.Optimize the design of protocol layer module by using the position of the state machine circuit which is unique to the synchronous word sequence in C-PHY high-speed transmission.The addition of table tennis operation module in the application layer module ensures the continuous data transmission,and the addition of special processing for VESA DSC data transmission ensures the normal operation of the later VESA decompression module.The digital circuit design in this paper uses Verilog HDL hardware description language to design and implement RTL-level code.After the circuit design is completed,n Lint tool is used to check the design rules and grammar.BFM simulation and verification platform is built using Verilog HDL language and shell language,the function simulation of digital circuit part is done using VCS tools,and the mixed simulation of digital and analog circuits is done using VCS and XA tools.According to the interface protocol and design specifications,a simulation plan is made to verify the correctness of the interface circuit function.It is concluded that the combined PHY structure can meet the dual-mode compatibility,and the C-PHY mode-related control circuit meets the design requirements.Based on the UMC 40nm process library,the design circuit is synthesized by the Design Compiler synthesis tool.The result shows that the area of the circuit is 84784μm~2 and the power consumption is 2.426 m W.The design circuit is optimized by Prime Time time series analysis tool,and the high-speed transmission rate can reach 1.1Gsps/Lane in C-PHY mode.