Study And Design Of MIPI DSI Interface Circuit

MIPI(Mobile Industry Processor Interface)is initiated by the MIPI Alliance to design and promote hardware and software interface,in order to simplify the integration of built-in components and to improve the compatibility of mobile devices.With the advantages of low power consumption and high data transmission rate,it is widely used in smart phones and tablets,It is a hot topic in this field.This thesis focuses on a MIPI high-speed interface circuit used in AMOLED driver chip,which consists of one clock channel and four data channels.Each channel contains high-speed data transmission and low-power instruction transmission.The speed of each data channel of the high-speed receiving module is up to 1GHz,and the speed can be up to 4GHz when four channels operate at the same time.High-speed mode and low-power mode can be freely converted according to demand,and the whole system can achieve a compromise between speed and power consumption.Starting with the whole structure of MIPI protocol,this paper introduces the four levels of MIPI,and focuses on the research and design of the key circuits in physical layer,such as high-speed receiving module,bias circuit module,low-power receiving module and so on.In the high-speed comparator,the improved current gain bootstrap amplifier is used to improve the gain of the comparator on the premise of ensuring the bandwidth,and the calibration circuit is used to ensure the accuracy of the high-speed comparator.In order to reduce the power consumption,the high-speed receiving module is turned on only when the high-speed data is transmitted,and the low-power receiving module begins to work when receiving instructions.The low power receiving circuit adopts the structure of hysteretic comparator to filter out the noise.Because the speed of MIPI interface will also be limited by the reading and writing speed of SRAM,which directly affects the refresh speed and display quality of the display image.Therefore,this paper studies and designs the key circuit of a high-speed and low-power SRAM circuit,including memory cell,sensitive amplifier,precharge circuit and read-write control circuit etc.t.The SRAM designed in this paper uses a group of four memory cells and a read-write control circuit to control the read and write of the memory in order to reduce the chip area and reduce the design complexity.At the same time,in order to improve the charging speed,the dynamic precharge circuit is used,and the latch sensitive amplifier is used for the reading andwriting speed of the data.All of the circuits in this paper are designed based on the process of UMC80 nm,the designed circuit is simulated on the Cadence Spectre.The simulation results show that the accuracy of the high-speed comparator is 5mV and the transmission delay is328.5ps,which meets the design requirements.The transmission speed of 1GHZ can be realized by single channel post-simulation of the high-speed receiving module.The results show that the MIPI circuit designed in this paper can achieve the data transmission speed of single-channel 1GHZ and low-power 20 MHZ,and can realize the conversion between high-speed mode and low-power mode on demand,which meets the design requirements.