Design Of A MIPI Protocol High-speed Interface D-PHY Physical Layer Circuit

With the rapid development of mobile Internet technology,the MIPI alliance has become the mainstream trend of development.It is leading the collaborative development of multiple fields in the semiconductor industry.MIPI protocol is a flexible source synchronous serial interface standard,including MIPI DSI protocol and MIPI CSI protocol.It can be used to connect the display module of the host and the camera module of the mobile device.At the same time,it has the advantages of high speed,low power consumption,low jitter and excellent anti-electromagnetic interference ability.In this paper,the MIPI physical layer directly affects the transmission rate and quality of the data signal.It plays a key role in the protocol.In the design of the clock channel,using a fully differential high-speed clock circuit design with duty cycle correction.It can ensure that the clock signal is transmitted from the sending end to the receiving end without loss,and the accuracy of data transmission is improved.This is an innovative point of this design.The clock correction circuit is mainly composed of a duty cycle detection module,a duty cycle correction module and a clock buffer.Among them,the duty cycle detection module adopts a folding cascode amplifier structure with simple structure,wide detection range and high detection accuracy.The duty cycle correction module adopts a combination of single-stage clock buffer and transconductance operational amplifier.The purpose is to achieve the goal of correcting the clock duty cycle.In the design of high-speed mode,it includes two parts that high-speed transmitter module and high-speed receiver module.Among them,the high-speed transmitter module is composed of a differential signal generator and an H-bridge NMOS bridge driver circuit.It uses a scalable low-voltage signal protocol to synchronously transmit differential high-speed data.The high-speed receiver module uses the very-wide common-mode range differential amplifier structure,which is an innovation of this design.It can receive high-speed data efficiently and stably,filter out additional noise,and at the same time introduce a linear amplifier in the output stage to increase the overall gain and shape the output waveform.In the design of low-power mode,it includes three parts that low-power transmitter module,low-power receiver module and low-power conflict detector module.Among them,the low-power transmitter module uses a combination of multi-stage push-pull drivers and weighted inverters.It can effectively limit the current,control the slew rate and reduce the dynamic power consumption.The low-power receiver module consists of a high reference voltage comparator,a low reference voltage comparator and an SR latch.It can improve the anti-electromagnetic interference ability,filter out spikes and burrs noise,achieve a better hysteresis effect.The low-power conflict detector module has a lower flip reference voltage,and it mainly used for products that require bilateral communication to detect channel status.This paper based on the MIPI D-PHY protocol,uses the SMIC 0.18μm CMOS technology to design a faster and better performance physical layer circuit.The simulation results of each module meet the requirements of the MIPI protocol specification.The duty cycle correction range of the clock channel is 20%-80%,and the error accuracy is ±0.5%.In high-speed mode,the single-channel signal transmission rate reaches 2Gbps,and in low-power mode the signal transmission rate is not more than 10 Mbps.The power consumption is 2.8m W,and the jitter is only 8ps,far less than the 32 ps required by the standard.