A Kind Of MIPI DSI Interface Design For FHD Display

With the rapid progress of information technology, smart phones and other portable devices become indispensable in people’s life. Technological advances also urge people to ask for high display effects. Big size high-resolution screens are becoming more and more popular. The display interface with high-speed transmission rate is becoming more and more important to display manufacturers. This paper introduces a kind of MIPI DSI interface designed for Full High Definition screen.This paper studies the MIPI Protocol. According to the requirements of FHD transmission, this paper comes up with the system architecture with double data lanes. The circuit of MIPI is divided into four layers according to the function. The four layers are PHY layer, lane management layer, low level protocol layer and application layer. The PHY layer module is mainly responsible for high-speed serial bit stream data reception, low power serial bit stream data reception and reverse data sending. The serial-parallel part of high-speed data reception circuit is adopted on the processing of the analog circuit for special treatment, in order to realize the requirement of high speed transmission. Lane management layer will merge dual lane data stream into single lane data stream. The function of the low level protocol layer circuit is decoding the received packets and sending the encoding packets. The high speed module in protocol layer deals with 16-bit data per time instead of 8-bit. This reduces the frequency of high speed clock. Dividing high speed and low power decoding circuits into two modules reduces the size of the high-speed decoding circuits. This makes it easier to satisfy the timing requirements. Reusing ECC module and CRC module will reduce the area of the verify circuits in low-power decoding module. The CRC module is dealt by parallel processing to avoid using the clock with higher frequency by serial processing. The application layer includes DPI and DBI circuits. The SPI configuration module is designed to improve the compatibility of the interface circuit.The modules in the paper is designed by Verilog and simulated by VCS. This design adopts the 90 nm process and is synthesized by Design Complier. This design uses Encounter to P&R. After simulation and verification, the layout is get with area 300μm×330μm and power consumption 8.16 mW.