| With the continuous development of mobile communication devices,people have higher requirements for mobile phone cameras and digital cameras.Increased bandwidth between camera and application processor is difficult for designers.This paper introduces a protocol standard based on MIPI CSI-2(camera serial interface 2),which provides a high-speed serial interface between hd camera and application processor.This paper mainly designs the high-speed data processing part of MIPI CSI-2.D-PHY protocol in high-speed transmission mode,the maximum signal transmission speed is 1.5Gbps.In this paper,the design is developed under the clock frequency of 750M of a single channel.Firstly,a two-sided edge trigger receiving circuit is designed to receive data correctly when the rising and falling edges are triggered.The final realization is that in four clock cycles,1 bit data is packaged into 8 bits data.The design difficulty is that under the 90nm process,the setup time of D flip-flop is longer than the clock cycle.The data processed correctly must be within the range reached by the clock rise edge after frequency division before it can be handed over to the next level of processing.Secondly,the receiving check module is designed,including lane merge,ECC and CRC.The channel management module packages four channels,each channel with 8bit data into 32bit according to the protocol requirements,analyzes the ECC packet header data and designs several additional control signals.ECC calibration module can achieve one error correction and two error checking function.CRC cyclic redundancy check module can realize the parallel check of 32-bit data with a period of 5.3ns.The parallel circuit implementation of its verification algorithm needs to match the data results given in the protocol.Finally,the time sequence optimization is accomplished by using the combination logic circuit with NOR-tree structure.Finally,ICC tool was used to complete layout design under the 90nm process.The two-sided trigger module is all composed of D flip-flop.After completing the layout,the final post-imitation result successfully achieves the target requirement.The second part is designed to receive and verify the module.The layout is pad limit.The area is mainly determined by the size of pad.Finally,both the VCS Backend emulation and the formal conformance validation achieve the design goals.The main contribution of this paper is to propose a receiver circuit solution under the 90nm process.This paper presents a circuit which can ensure the correct reception of data only in high speed mode,including a design scheme of how to control the start and end of the circuit. |
