Design Of 14 Bit 250 KS/s SAR ADC With Digital Background Calibration

Analog-to-Digital Converter(ADC)is a key module unit in System on Chip(So C),which plays a vital role in electronic systems.Compared with other types of ADCs,the circuit modules in Successive Approximation Register(SAR)ADC are mostly digital circuits,which have the advantages of high integration,low power consumption and small area,and is widely used in wearable intelligent sensors,biomedical electronics and other fields that need medium-high precision ADCs.However,the mismatch of the capacitor array limits the improvement of its accuracy,SAR ADC with single structure can no longer meet the design requirement of high accuracy.Therefore,it is necessary to take advantage of the easy integration and better effectiveness of digital background calibration to effectively improve the nonlinearity problem caused by capacitor mismatch.To address the problem that capacitor mismatch degrades the accuracy of SAR ADC,this paper designs an effective digital background calibration algorithm to improve the problem.Firstly,the principle of SAR ADC and the capacitor mismatch error are analyzed,the linearity of ADC is reduced by capacitor mismatch in detail,and the calibration algorithms of different implementations are summarized.Then,based on the MATLAB software platform,the digital background calibration algorithm based on"Split"structure and a perturbation-based digital background calibration algorithm are designed and compared.Compared with the former,the latter algorithm is implemented with single-channel SAR ADC,which reduces circuit power consumption and avoids gain error between channels.On this basis,a 14-bit SAR ADC with a perturbation-based digital background calibration algorithm is designed,and the weights of this ADC will be updated iteratively by the Least Mean Square(LMS)algorithm.In this design,the relationship between the number of quantization,curve convergence and calibration effect are considered in a compromise,and the appropriate value is selected according to the simulation results.Finally,the SAR ADC and calibration algorithm are designed and simulated through Cadence and Modelsim software platforms respectively,and the correctness and effectiveness of this design are fully verified by comparing with MATLAB simulation results.A 14-bit SAR ADC for intelligent sensor applications is designed in this paper,based on a180 nm CMOS process,the overall circuit design,layout design with IO loops,and post simulation considering parasitic parameters are completed.By adding a perturbation-based digital background calibration algorithm,the Effective Number of Bits(ENOB)of the designed ADC can be increased from 10.88 bit to 12.55 bit at a sampling rate of 250 k S/s under a 1.2 V supply voltage,and the Spurious Free Dynamic Range(SFDR)and Signal to Noise and Distortion Ratio(SNDR)can be increased from 73.7 d B and 67.3 d B to 100.3 d B and 77.3 d B,respectively,and the whole calibration process can reach stable convergence after 40000samples.Figure of Merit(Fo M)of the ADC is 47.5 f J/Conversion-step,and power consumption is 71.2μW,the core area is 0.5682 mm~2,of which the core area of analog is 0.3826 mm~2,and the core area of digital background calibration algorithm is 0.1856 mm~2,which is very suitable for low-voltage high-precision application scenarios.