A High-speed And High-precision Time-interleaved Analog-to-digital Converter Using A Novel Mismatch Calibration Algorithm

With the development of the integrated circuit manufacturing industry,the speed of digital signal processing is rapidly increasing.As a bridge connecting the analog world and the digital world,the analog to digital converter(ADC)has been continuously improved in its sampling rate and precision requirements.High-speed and high-precision ADCs have important strategic significance and are in great demand in high-end military and civilian equipment,they are scarce in chips.The domestic research on high-speed and high-precision ADC started late,and there is a big gap with the international leading level.At the same time,the key technology has been blocked by the United States.Research in this field is of great significance.Time interleaving is a common architecture to achieve high speed and high precision.It can double the sampling rate of ADC by stacking the number of channels.In the selection of single-channel ADC,pipeline ADC can maintain high precision at a higher sampling rate,this thesis will systematically study the key technology of time-interleaving pipeline ADC.Based on 40 nm CMOS process,this thesis designs and implements a 12 bit 1GSps4-channel time-interleaved pipelined ADC.This thesis firstly studies the key technologies of pipelined ADC,expounds the basic architecture and principle of pipeline ADC,determines the pipeline ADC architecture of single-stage 3-bit SHA-less architecture combined with inter-stage gain calibration technology,then the sample-and-hold circuit,Sub-ADC and MDAC of a single pipeline stage are analyzed and designed.Then this thesis studies the key technology of time-interleaving ADC,expounds the basic principle of time-interleaving structure,studies and designs the clock control method of using frequency divider to generate 4-phase clock,the three main types of mismatch,including offset mismatch,gain mismatch and time skew,are introduced in detail,and the effects of these three types of mismatch in the frequency domain are calculated and deduced.After analyzing the advantages and disadvantages of various calibration techniques,a background calibration algorithm is proposed to achieve convenient cumulative average extraction of mismatch values and directly eliminate them at the output.In this thesis,the background calibration algorithm of digital domain extraction and analog domain compensation is selected for implementation and improvement.The pre-simulation result of this design single-channel pipeline ADC is: SNDR is81.8dB,SFDR is 91.8dB,the post-simulation result of this design first four stages' parasitic is: SNDR is 81.8dB,SFDR is 91.8dB.The analog circuit part of the 12bit1 GSps 4-channel time-interleaving pipeline ADC has been verified by the pre-simulation,and its SNDR is 81.2dB and the SFDR is 91.2dB.The calibration technology for mismatch calibration has been verified by simulation to effectively suppress the spurs caused by mismatch.Separately,the performance before and after offset mismatch calibration can be improved by 31.4dB,the performance before and after gain mismatch calibration can be improved by 34.4dB,and the performance before and after sampling time mismatch calibration can be improved by 20.3dB.In addition,the sampling time mismatch calibration algorithm optimized by this thesis has faster convergence and more accurate accuracy than the traditional method.