The Research And Implementation Of The Digital Background Calibration Algorithm For Pipelined Analog-To-Digital Converters

Analog-to-Digital Converter is a device that analog signal can be transformed to digital signal. It is a bridge to connect analog signal and digital signal. In many types of ADCs, Pipeline ADC which has high speed, high precision and high resolution is widely used in signal processing system. Such as fast Ethernet, wireless communication system, digital receiver, digital video, etc.However, with the size of CMOS technology gradually reducing and the voltage of power supply decreasing, Pipeline ADC will be affected by limited op-amp gain and capacitor mismatch, etc. These non-ideal factors make the design of analog circuit becomes more difficult. Because of the digital circuit system of high stability, good reliability, the advantages of no static power consumption and small area, making digital calibration technology become essential in the design of higher performance ADCs. In many kinds of digital calibration techniques, the digital background calibration techniques which can greatly improve the system speed is most widely applied in recent years.Through to the infrastructure principle of pipeline ADC, and based on the analysis of all kinds of non-ideal factors, this thesis introduced a digital background calibration algorithm based on pseudo-random sequence signal, which is used to correct the non-linear error of pipeline ADC caused by the limited op-amp. This way is that by adding harmonic distortion function in the first level of pipeline ADC to simulate the limited amplifier gain. The nonlinear effect will eventually be seen in the digital output code. Then using the correlation and no correlation with other sequences of PN sequence itself, error coefficients are extracted from the digital output signal. Then digital output signal without calibration will be compensated to achieve the right digital output. At the same time this thesis also optimize digital calibration algorithm by piecewise accumulative for average for extraction of error coefficient, which reduces the complexity of circuit and improve the speed of the system. Through the simulation, this thesis is under 100 MHz sampling clock frequency, the input sine signal frequency is 1.01318359375MHz, after the background of digital calibration algorithm of pipeline ADC, Signal-to-Noise and Distortion Ratio is improved from 46.87dB to 76.27dB, Spurious Free Dynamic Range is improved from 53.66dB to 83dB.