Digital Background Calibration Of12bit High Speed Pipelined ADC

Data converters are the interface between analog world and digital domain processing,therefore ADCs (analog to digital converter) are indispensable in current electronicssystems. After comprehensive analysis of various ADCs, we choose pipelined ADCs, whichare widely applied in high speed and high resolution field, as the topic of this thesis.Several non-ideal factors are introduced according to references, for example, the offset ofcomparator, capacitor mismatch, charger injection in a switch and op-amp errors. In recentyears, many calibration methods are published. A new digital calibration with two-ditheringis proposed refer to the methods using pseudo random numbers.The purpose of the proposed digital calibration is to remove the errors due to capacitormismatch and finite op-amp gain. In this scheme, two uncorrelated pseudo random signalsare injected in to the signal channel. Since the pseudo random numbers are uncorrelatedwith zero mean signals but correlated with itself, a approximate value of the errors can bedetected by correlating the digital residue output against pseudo random numbers. Anadditional sample capacitor is applied in the calibration, and in order to convert harmonicdistortion into white noise, the dynamic elements matching (DEM) methods is used in thispipeline ADC. The residue output is calibrated in digital domain. A12bit100M/s pipelinedADC with capacitor mismatch error and finite op-amp gain error is modeled by MATLABtoolbox. Two pseudo random signals are injected, and the calibration method is executedusing simulink. the outputs before and after calibration are measured respectively。Dynamic performance and statistics performance of pipeline ADC outputs before andafter calibration are calculated. The effect number of bits is improved from7.474bit to11.933bit. And for the statistics performance, instead of87missing codes due to errors, theDNL is increased to+0.41/0.31LSB, INL is improved from+17/17LSB to+0.29/0.29LSB. Requirements of op-amp and other circuits are calculated according tothe purpose performances of pipelined ADC. The key modules have been designed basedon0.18μm CMOS process.