A 14 Bit Low Power SAR ADC With Analog Background Calibration

With the miniaturization and portability of biomedical equipment and with the development and popularization of wearable equipment,the acquisition,quantification and feature extraction of bioelectrical signals become very important.In order to obtain accurate bioelectric signal for feature extraction,high accuracy is crucial;as a result of the limitation of battery power,low-power design is needed.As a key module of the signal acquisition system,ADC(analog-to-digital converter)occupies a large part of the power consumption,and in all ADCs with different architectures,the SAR ADC(successive approximation analog-to-digital converter)has a good compromise between power consumption and accuracy,making it ideal for medium to high precision and low power applications.In this paper,a novel analog background calibration algorithm is proposed and a 14-bit low power SAR ADC with this calibration algorithm is implemented in the CMOS 40 nm process.First of all,for the charge redistribution SAR ADC,the matching accuracy of the capacitor is very important to the linearity of the system.as a result,capacitor mismatch is one of the important limiting factors to realize the medium to high precision SAR ADC,so the capacitor mismatch calibration algorithm is indispensable.This paper investigates three main algorithms of capacitor mismatch calibration,including analog foreground calibration algorithm,analog background calibration algorithm and digital background calibration algorithm,analyzes their principles and compares their advantages and disadvantages,and according to the application environment of this design,a novel analog background calibration algorithm is proposed.After MATLAB modeling and circuit implementation,it is verified that the calibration algorithm can eliminate the influence of capacitor mismatch on the linearity of the system,and meet the design requirements of 14-bit SAR ADC.Secondly,the linearity of the sampling switch and the accuracy of the comparator are also the main factors that limit the linearity of the system.Therefore,the bootstrap structure is adopted in the SAR ADC to improve the linearity of the on-resistance of the sampling switch and the linearity of sampling,at the same time,the structure of the comparator is composed of two stages: a two-stage preamplifier and a Latch,which reduces the noise of Latch and the input offset voltage.Finally,in order to meet the biomedical application environment,a series of measures are taken to reduce the system power consumption.For example,0.8V low-voltage power supply is utilized in this SAR ADC;DAC adopts the Vcm-based structure,which reduces the capacitance of the capacitor array and the number of DAC switching and power consumption;clocked comparator is used in this paper;digital logic utilizing stack structure reduces the leakage of current.Based on the HSPICE simulation results,the SAR ADC achieves a SFDR of 94.1 dB,a SNDR of 80.8 dB,and an ENOB of 13.1 bits at 300 kS/s,the power consumption is 19.047 ?W,resulting in a FoM of 7.23 fJ/Conversion-step with 0.8V power supply.