Research And Design Of A SAR ADC With Capacitor Mismatch Calibration

An analog-to-digital converter is a circuit that converts analog signals into digital signals.It is widely used in wireless communications,sensor networks,optical communications and other fields.In recent years,successive approximation analog-to-digital converters have become a research hotspot due to their simple structure and low power consumption.The performance of SAR ADC is restricted by various non-ideal factors.Among them,CDAC capacitance mismatch is one of the main factors affecting the actual quantization accuracy of SAR ADC,so it is of great practical significance to calibrate the capacitance mismatch of CDAC.In this thesis,SAR ADC is studied and a 12-bit SAR ADC is designed.This design uses a bootstrap switch to reduce the nonlinearity during the sampling process.The CDAC uses Split-Capacitor switching scheme,and it includes one redundant bit.The redundant bit provides error tolerance for quantization.The SAR ADC uses an offset calibration technique that can accommodate offset within a certain range.The SAR ADC uses a capacitor mismatch calibration technique based on comparator metastability detection.This calibration technique takes advantage of the characteristics that the low-bit quantization results can be expected when metastability happens.The ideal quantization result is subtracted from the actual quantization result,and the average value is calculated multiple times to obtain the weight value of the capacitor mismatch.The realization of this calibration technique requires the SAR ADC to collect a sufficient number of metastable points in the calibration mode.The metastability detection range and the number of metastable points are important factors that affect the effect of calibration.This design includes a metastability detection circuit,which judges whether the metastability happens by comparing the delay of the comparator with the delay of the tunable delay circuit.The metastability detection circuit utilizes the characteristic that the voltage of the upper plate of the CDAC is gradually approaching in the quantization stage to judge whether the metastability detection range meets the requirements and make adjustments.This design is realized under the 40 nm CMOS process.The previous simulation results show that under the tt corner,when the sampling rate is 150 MHz and the input signal is a full swing sine wave of 37.64 MHz,the ENOB is 11.98 bit.The layout size of the SAR ADC is 510?m×422?m.The post-simulation results show that under the tt corner,when the sampling rate is 100 MHz and the input signal is a full swing sine wave of 25.39 MHz,the ENOB is 11.52 bit.At a sampling rate of 100 MSps,the total power consumption of the SAR ADC is 6.391 mW.