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Techniques For High-resolution SAR ADCs' Digital Calibration

Posted on:2022-03-10Degree:MasterType:Thesis
Country:ChinaCandidate:Y H DuFull Text:PDF
GTID:2518306524977459Subject:Microelectronics and Solid State Electronics
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With the development of integrated circuits and technology,the speed and integration of ICs are increasing rapidly.As a type of circuit that directly benefits from technology development,digital circuits are favored by the majority of investors.However,signals in nature are always analog signal.In order to convert continuous signals into discrete signals,digital-to-analog converters have been proposed.Among them,high-resolution SAR ADCs are widely used in medical instruments,wireless communication systems,and imaging systems because of their high energy efficiency.The accuracy of high-resolution SAR ADCs is mainly limited by the capacitance mismatch.Without mismatch calibration,the ENOB of SAR ADCs can hardly exceed10 bits.Therefore,in this paper,the basic knowledge of SAR ADC is summarized,and the influence of various non-ideal factors on the accuracy and linearity is explained in detail.Based on the existing SAR ADC calibration algorithm,this paper proposes a digital background calibration algorithm based on Split-ADC.The calibration algorithm uses the LMS algorithm to iteratively solve the capacitance mismatch error,so there is no need to know the accurate capacitance value,and the influence of noise on the convergence result is reduced.The calibration algorithm is verified by MATLAB modeling and simulation,and the relevant convergence coefficients are optimized.In this paper,a 14-bit 4 MS/s SAR ADC is proposed under 40 nm process in 1.1 V voltage domain.The circuit design process of each module are introduced in detail,and the performance is optimized separately.After artificially adding capacitance mismatch,it is combined into an overall circuit for simulation,and the obtained output code is brought into the calibration algorithm.After the calibration,the ENOB of the ADC is 12.37 d B.The SNDR and SFDR have reached 76.23 d B and 98.57 d B,respectively.The power consumption of the overall circuit is 78.4 ?W...
Keywords/Search Tags:high-resolution analog-to-digital converter, successive apporoximation register, capacitor mismatch calibration, split analog-to-digital converter, digital background calibration algorithm
PDF Full Text Request
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