Design Of Anti-Variation Clock Tree Based On Near-Threshold Timing Modeling Method

With the development of process nodes,the scale of digital circuits has also grown exponentially.The increase in transistor density has caused a sharp rise in circuit power and heat.Based on this,low-power design has become the main direction of digital integrated circuit design.Designers usually reduce the power supply voltage to achieve the goal of reducing the total power of circuit.However,under near-threshold voltage regions,the delay of metal interconnect and clock units increases.Besides,the impact of process variations is also amplified,resulting in increased circuit clock skew,which causing the setup and hold time violations.In order to solve the above problems,a clock tree timing modeling method for nearthreshold voltage circuit is adopted in this thesis,and an improved robostness clock tree construction strategy is proposed.The clock tree timing model in this thesis is composed of clock cell model,interconnect model and clock path model.First,the process variation factors of clock units and metal interconnects under deep sub-micron process will be analyzed,and the influence of process parameter vavriations on cell and interconnect delay and Slew will also be analyzed.Then delay,delay variation,Slew and Slew variations will be modeled using a regression fitting algorithm which is composed of the Levenberg-Marquardt algorithm and the Simulated Annealing algorithm.Finaly,the clock path model will be modeled by calculation which uses the clock cell model and the interconnect model.Based on the obtained timing model,a clock tree construction strategy named DP+DME is proposed.The input of the algorithm is skew constraint,slew constraint and timing model file.The clock tree topology is constructed through two processes of bottom-up solutions generation and top-down solutions selection.In this thesis,the proposed near-threshold clock tree timing modeling method and clock tree construction strategy are validated on the ISCAS89 benchmark circuits(S35932 and S38584)and the Cortex-M3 benchmark circuit with SMIC40 LL process.The results show that compared with the clock tree obtained by EDA tool(IC Compiler),the method proposed in this thesis optimizes the clock skew of by 35.1% on average,and the clock skew variation(standard deviation of clock skew)by 37.3% on average and the operating efficiency is also improved.Compared with the benchmark literature,the method in this thesis optimizes the clock skew by 37.07% on average,and the clock skew variation by 26.43% on average.