Research And Implement On Clock Tree Structure Under Low Voltage

After the chips working voltage reduced, the performance of the circuit will be challenged. When the voltage drop to near threshold voltage or even below threshold voltage, current provided by circuit is closely related to the threshold voltage. The jitter of threshold voltage caused by the process variation will become the main factor, which affecting the circuit performance.This paper puts forward a method of resistance process variation clock tree design under low voltage, mainly divided into three parts:1) Pre-CTS layout optimization; 2) consider the process variation of the clock tree structure design; 3) the clock tree structure optimization. In the Pre-CTS placement optimization, the number of clock tree branches is reduced through register group. Considering process variation of the clock tree structure design, by choosing different threshold devices, and reduce branch, the performance of clock network is more stable. In the optimization stage, by the method of the size-down, adjusting the size of the buffer unit, clock skew is optimized.Resistance to process variation of clock tree structure design under ultra low voltage design in this paper, is implement and verify in two designs, GPS tracking module and a embebdded CPU circuit. The results show that the design of the clock tree designed in this paper has the same performance compared with the EDA tools under normal voltage. Under low voltage, the ability of process deviation resistance is increased by 45.5% for GPS tracking module and 40.96% for the embedded CPU.