Analysis And Research On Clock Tree And Timing Optimization Based On 40nm Process MCU Chip

With the rapid development of the integrated circuit industry,the scale and frequency of the digital IC design are improved and the clock structure is getting more and more complex.The clock signal is the datum for data signal transmission,and the quality of the clock tree directly determines whether the MCU can achieve timing closure,so clock tree synthesis(CTS)and timing optimization play an important role in the back-end design.The result of the clock tree not only affects the timing,but also affects the power consumption of the design.Based orn MCU chip with TSMC 40nm process,this paper utilizes ICC2 of Synopsys to complete the placement and routing.The gates of the MCU is about 6.18 million and the highest frequency is about 180MHz.The MCU can be used for intelligent wear and intelligent medical fields.According to the requirements of the MCU,a new layout scheme is proposed,which combines the power domain distribution with the site array.The results demonstrate that the solution can relieve effectively wiring congestion that is acceptable.What's more,it meets the requirements of timing and area.This paper emphasizes that the power consumption of clock network can be reduced while improving timing results.To meet the requirements of the MCU,several CTS strategies are proposed:(1)The traditional CTS is subdivided into CTS,clock tree optimization(CTO),clock tree balance(CTB)and clock routing,which can be corrected by the results of each phase;(2)Different combinations of buffers and inverters are used to perform CTS,CTO and CTB;(3)Analyzing the structure of clock tree,selecting th e key clock elements,and manually contigurmg the clock elements.The results show that CTS strategies which are proposed in this paper would improve the quality of clock tree:(1)Reduce the clock latency to about 5.78%-92.54%of the original value;(2)Depress the clock skew by 0.52%-77.06%;(3)The total number of setup violations is lowered to 51.79%,and the value of violation is lowered to 52.80;(4)The total number of hold violations is reduced to 68.07%,and the value of violations is reduced to 70.00%;(5)Clock network power consumption is decreased to 83.85%,and total power consumption is decreased to 99.060%.