Design And Implementation Of Low Voltage Process-Variation-Tolerant Clock Tree

Along with the rapid advances in very large-scale integration technology and semiconductor technology, the advent of IOT (Internet of Things) fuels the requirements of low power circuits. Supply voltage scaling is one of the most well-known methods to achieve low power systems. As the supply voltage is scaled, the circuits become more susceptible to process variations. A clock tree is typically the largest net in the circuit, process variations tend to have significant negative impacts on the clock tree. Thus with the low power requirements, the clock tree should be well designed against process variations to avoid functional failures.In this thesis, a process-variation-tolerant clock tree design methodology at low voltage is investigated. It mainly includes:1) all registers having direct or a transitive timing relationship between each other are placed within the same cluster and they share the most clock buffers and clock nets along associated clock paths in the clock tree, while the commonly shared clock path up to a common point does not contribute to clock skew variation; 2) a process-variation-tolerant clock tree topology is designed, and a semi-customed parallel clock inverter is applied in the process of clock tree synthesis, thus levels and branches of the tree are reduced and the robustness against process variations is improved; 3) In the process of clock latency and skew optimization, firstly the whole clock cells are sized up to maximum to improve robustness, then the delay of some clock paths is relaxed by sizing down clock cells to meet clock skew requirements.The robustness against process variations of clock tree is tested and analyzed based on ISCAS89 benchmark circuits, a GPS tracking circuit and an embedded microprocessor at low voltage. Results show that compared with traditional backend design method, the standard deviation of clock skew in ISCAS89 benchmark circuits, the GPS tracking circuit and the embedded microprocessor are reduced by 41.15%, 56.47% and 42.61% respectively.