Register Grouping Design For Anti-process Variation Clock Tree Under Near-threshold

In the design of digital integrated circuit,reducing the voltage can effectively reduce the power consumption of the clock tree,which is an effective way to realize the low power consumption of the chip.However,when the voltage is reduced to the near threshold voltage,the clock unit is affected by the process fluctuations and the clock path delay is prone to uncertain changes,which will increase the clock deviation of the clock tree,reduce the circuit performance,and even cause functional errors.Therefore,it is necessary to pay attention to the anti-process fluctuation ability of the clock tree and enhance the temporal stability of the clock tree when the threshold voltage is near.On the basis of analyzing the clock tree design problem under near-threshold voltage,this paper puts forward a register clustering scheme driven by timing and balanced by load,which is used to design clock tree against process variations.This project mainly includes the following aspects: 1)divide the registers into multiple groups by time-series-driven register grouping,increase the public path of time-series-related registers on the clock tree topology,and reduce the influence of delayed fluctuations on the timing on the non-public path.2)group load balancing algorithm is used to optimize the results of time series grouping,and smaller register groups are merged to achieve load balancing among the resulting register groups,which is conducive to the realization of balanced clock tree topology.3)allocate the clock buffer of the maximum size for each group,increase the anti-process fluctuation ability of the clock tree,then reduce the delay difference of the leaf buffer by adjusting the buffer size,and finally reduce the clock deviation of the generated clock tree.In this paper,the anti-process fluctuation clock tree design method based on register grouping is compared and verified with the traditional clock tree comprehensive process on ISCAS89 reference circuit and ARM Cortex M0 and M3 microprocessor.The clock tree is simulated by Monte Carlo through HSPICE,and the clock deviation and standard deviation of the clock tree are obtained.For the four circuit modules in ISCAS89 benchmark circuit,the clock deviation and standard deviation were decreased by 21.63% and14.54% on average.For the ARM Cortex M0 microprocessor,the clock deviation and standard deviation of HCLK were decreased by 21.44% and 39.28% respectively,and the clock deviation and standard deviation of DCLK were decreased by 15.50% and 8.58% respectively.For the ARM Cortex M3 microprocessor,the clock deviation and standard deviation of HCLK were reduced by 9.11% and 15.52%,respectively,and the clock deviation and standard deviation of FCLK were reduced by 55.22% and 42.13%,respectively.