Design Of The Buffering Strategy For Clock Trees Under Near-Threshold-Voltage

There are two steps,namely topology design and buffering,in the near-threshold-voltage(NTV)clock tree synthesis.Under NTV,the delay and its variation of transistor dramatically increased compared with it under normal voltage.To implement more high-performance clock tree design in this scenario,symmetrical clock tree topology is preferred in the topology design step.And buffering become a key stage to further explore more robust clock tree optimization.In most related work,buffering is an insertion point optimization process based on the limited buffer size,which will narrow the solution in the buffering variation optimization.Buffer-library-oriented buffer size and buffer insertion location co-optimization can hopefully get more robust clock trees.Based on this opinion,this work implements a buffering strategy for NTV clock tree synthesis.In this strategy,buffer-library-oriented buffering is carried out based on the very symmetrical un-buffered clock tree topology and is formulated as an integer programming problem to minimize clock tree skew variation.The modeling method is based on the symmetrical clock tree skew estimation formula and then applied to this problem by introducing the coefficient matrix of buffer delay(,)between different sizes.The modified mathematical formula represents the optimization objection during buffering and is later solved by the generic algorithm(GA).The insertion solution is obtained after iteral generations,which represents the buffer's insertion point and buffer size in each clock path.The experiment is carried out based on 4 different open-sourced benchmarks from opencores website with standard cell placement finished by IC Compiler,in SMIC 40nm PDK.Then,the proposed buffering strategy combined with topology generation is applied.Finally,clock tree skew and its variation are obtained by spice simulator under 0.6V.The result shows that,compared with commercial tool IC Compiler 2016.03,₆0)),₆0))are reduced by21.69%,7.7%respectively.Buffer area is reduced by 6%.Compared with DP-DME,on the other hand,₆0))is reduced 31.2%while₆0))increased by 8%?The complexity of overall flow is reasonable compared with produced DP-DME.