Dynamic Reconfigurable Clock Tree Design Methodology For Wide Voltage Scaling

Wide voltage scaling can reduce power consumption and has little impact on performance,and the near-threshold region is often chosen as the low voltage mode because of its high energy efficiency.However,it results in problems for clock tree design as follows: First,device delay increases as voltage decreases.It is hard for a fixed clock tree to maintain the balance between interconnect delay and device delay when voltage changes,resulting in an increased clock skew.Secondly,the clock tree is also more sensitive to process variations in the near-threshold region.Process variations incur random fluctuations in clock latency and increase the random skew.In order to solve the above problems,a dynamic reconfigurable clock tree using custom bypassable buffer is adopted in this thesis,and an improved custom buffer and a fast virtual clock tree synthesis methodology are proposed.First,the structure of the custom buffer is improved.The buffer propagation delay model is qualitatively established and the working states are analyzed to guide the parameter selection.Then a fast virtual clock tree synthesis methodology is proposed.Combined with electronic design automation(EDA)tools and algorithm for buffer sizing and configuration optimization,it can obtain a quasi-optimal configuration of the reconfigurable clock tree.After comparing the Monte Carlo simulation results with mutation configuration,the configuration with the smallest random skew is selected as the optimal configuration to establish the look-up table.In this thesis,the proposed methodology is validated on ISCAS 89 and Opencores benchmarks with SMIC 40 nm LL process.As the results show,compared with the conventional clock tree synthesized by EDA tools,the proposed clock tree reduces the clock skew and the random skew by an average of 28.85% and 28.92% respectively,and the buffer area overhead increases by an average of 0.83%.Compared with the benchmark literature,the reconfigurable clock tree proposed in this thesis improves the random skew ratio of the conventional clock tree to the reconfigurable clock tree by an average of 11.72%.