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Implementation Of Near-threshold Circuit Timing Analysis Method Under Process Variation

Posted on:2020-11-15Degree:MasterType:Thesis
Country:ChinaCandidate:J P WuFull Text:PDF
GTID:2428330623959776Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Near-threshold circuits have received extensive attention due to its energy efficiency advantages.With fully considering the delay distribution under process variation,statistical timing analysis is suitable for near-threshold circuit timing analysis,but it faces difficulties: Firstly,the cell delay is nonlinear with the process parameters in near-threshold,which makes it difficult to statistically model the cell delay through process parameter distribution.Secondly,the correlation between the cell delay in the path makes it difficult to statistically model the path delay by the cell delay distribution.In the above background,a delay statistical model is established based on lognormal distribution for the cells and paths of near-threshold circuit.As for the cell,firstly,the statistical inverter delay model is established based on the gauss distribution of threshold voltage;Secondly,to solve the problem of multi threshold voltage variation in stacked and parallel structure,the equivalent threshold voltage and the equivalent current statistical moment is proposed respectively,and the statistical model of the combined logic cell delay is established.As for path,the path delay statistical model is established for both fast/slow input(input transition time is less/more than twice of cell delay in the path).For fast input,the path delay statistical model is established on the proposed path delay combinational characterization method based on the cell delay variation source decomposition.For slow input,the path delay statistical model is established on the fitting cell delay variance.The proposed cell and path model has been verified in TSMC28 nm process and near-threshold voltage.The results show that compared with the Monte Carlo simulation results,the average error of the model testing through combinational logic cells and ISCAS99 test path is less than 12% and 10%,respectively.The accuracy of the cell delay variance in the stacked and parallel structural models based on multivariate variables equivalence has improved to 3.25 and 3.35 times comparing with the nominal delay equivalence method;The accuracy of the path delay variance of the proposed path model has improve to 1.99 times comparing with the fixed correlation method.
Keywords/Search Tags:near-threshold circuits, statistical timing analysis, process variation, analytical delay model, lognormal distribution
PDF Full Text Request
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