Design And Research Of Test Chips For Threshold Voltage Variation Monitoring Of Transistors

Nowadays,the development of Integrated Circuit(IC)has entered the nano-meter age;and design rules,manufacturing technologies and process flows of IC become very complicated.As IC feature size continues to shrink,the manufacturing technology of IC satisfies people's needs for high performance and low power consumption of function chips,but process variation in the IC manufacture process has gradually become a vital factor affecting chips'reliability and stability.Especially,threshold voltage(Vth)of a transistor is very sensitive to WID process variation.The threshold voltage of a transistor is a critical parameter to characterize the performance of the transistor,the Vth variation affects the robustness of function chips to an extent.A test chip for monitoring the threshold voltage variation of transistors,not only can measure the Vth variation of transistors for foundries but also is helpful to achieve real-time monitoring of function chip reliability and stability for fabless IC companies.This thesis proposes a test chip monitoring the Vth variation of transistors based on the exponential relationship between sub-threshold leakage current and threshold voltage.Utilizing an oscillation structure,the chip establishes the relationship between threshold voltage variation of a transistor,sub-threshold leakage of the transistor and periods of pseudo-ring oscillation.By sequentially selecting DUTs in the pseudo-ring oscillation,the period variation of pseudo-ring oscillation can be acquired,in order to obtain the threshold voltage variation of the transistor with a corresponding size.The design mainly takes care of the aspects for achieving small area,low power,and high accuracy monitoring as follow:(1)Introducing an addressable circuit design based on a counter;(2)Introducing a method,in which the gate of every DUT is applied a weak bias to make the sub-threshold voltage leakage current dominant and make the leakage current of DUT much larger than that of pull-up or pull-down network;(3)Introducing a block-based method to estimate the equivalent systematic error.The test chip is implemented in SMIC 55nm process.Simulation results show that the measurement accuracy is within±3m V and when supply voltage is within±0.1V,the voltage variation has no influence on the measurement accuracy of the test chip.The test chip achieves Vth variation monitoring of transistors with two sizes,whose total area is 378)~2 and power consumption is 70nW at 1.2V operation.