| Near threshold voltage(NTV)operation of logic can improve energy efficiency by an order of magnitude.However,clock skew increases rapidly because of the increase of the insertion delay.Clock skew variation also increase,which reduce robustness of the circuit.Therefore,it will make great sense to optimize clock skew at NTV clock network design.In statistics static timing analysis,clock skew is represented by mean and clock skew variation is represented by standard deviation.Clock skew variations were not taken into consideration at traditional methods.Additional clock skew variation constraint was proposed to control clock skew variation at previous works,but buffer optimization is not considered.Optimizing clock skew and clock skew variation with a small power overhead is the major problem in this paper.A clock tree with highly symmetrical structure like H-Tree can greatly reduce clock skew but wire length increases rapidly.Since wire delay can be ignored at NTV because of the low delay ratio we don't put the wire symmetry into consideration but only consider clock buffer symmetry to reduce wire length.According to this feature,a balanced clock tree structure is proposed at NTV which buffers on each path are symmetrical to reduce the clock skew.Moreover,a dynamic programming algorithm is introduced to optimize the size and number of clock buffers which to reduce the clock skew variation and power consumption.The clock tree synthesis algorithm proposed in this paper is implemented on ISCAS89 benchmark and ARM Cortex M0 circuits.The mean and standard deviation of clock skew are obtained by Monte Carlo simulation.Experiment results show that our algorithms reduce mean of skew by 41.9% and standard deviation of clock skew by 5.3% with 1.1% power consumption and 123.9% run time increase compared with DP+DME,reduce mean of skew by 26.7% and standard deviation of clock skew by 21.3% with 8.4% power consumption increase and 69.2%run time decrease compared with ICC. |
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