Design Of A High Frequency Gated Clock For Single Photon Detection System

The single photon detection system based on avalanche photodiode(APD)is often used in laser ranging,detection imaging and quantum communication,and has broad application prospects.As a control method of fixed time sequence single photon detection,narrow gated forced quenching can realize the application of key transmission in quantum communication.In this system,a square wave gated clock signal with high swing and frequency of more than 1GHz is often required to control the switching of APD working state to achieve high-performance detection of low photon leak rate,low dark count rate and low post pulse.In order to meet the needs of single photon detection system,two high-frequency clock circuits for single photon detection are designed based on frequency-locked loop(FLL),which are self-biased first-order FLL and reference clock input second-order FLL.As self-biased first-order FLL,a frequency-voltage-converter(FVC)and a voltage controlled oscillator(VCO)are used to form a loop,determines the output frequency through the intersection of their tuning curves,and adds a programmable frequency divider between them to realize the fine-tuning of the frequency.The second-order FLL system of reference clock input type converts the input frequency and feedback frequency into voltage through the FVC.Then after error amplification,the output control voltage is used to adjust the output frequency of VCO,and the frequency division ratio is changed by the programmable frequency divider to realize the frequency doubling function of input reference frequency.The frequency-voltage-conversion circuit,which combines charge sharing and switching resistance,can effectively reduce the ripple amplitude of the conversion voltage and reduce the output clock jitter.The VCO adopts a two-stage ring structure composed of fully differential delay units to improve the output frequency,complete the modeling and analysis of its phase noise,and reduce the output phase noise to the greatest extent combined with the loop model.The overall loop adopts 1.8V device design to reduce power consumption,and the output stage adopts level shift circuit to realize the swing transformation of GHz signal from 1.8V to 5V.This article is based on TSMC 0.18 μm standard CMOS process,complete the circuit parameter design,system layout drawing and pre and post simulation verification on cadence platform.The post simulation results show that the output frequency range of self biased FLL system is0.79GHz～1.13 GHz.At the typical frequency of 1GHz,the duty cycle of 1.8V/5V clock is 50.5%/49.8%,the peak-to-peak jitter is 4.75/5.95 ps,the core power consumption of the circuit is 19.4m W and the power consumption of system is 95.5m W.The output frequency range of the second-order FLL system is 0.80GHz～1.20 GHz.Under the typical frequency of 1GHz,the duty cycle of the1.8V/5V clock is 50.5%/49.8%,the peak-to-peak jitter is 1.54/3.04 ps,the core power consumption of the circuit is 20.2m W and the power consumption of system is 96.9m W.Both schemes can meet the requirements of single photon detection gated clock.