Study And Design Of A Lower-Voltage, Lower-Power, Higher-Stability CMOS Phase Locked Loop

PLL frequency synthesizer is increasingly used in microprocessor systems and communication. With the development of integrated circuits and the emergence of SOC (System on a Chip) technology, it has been a fundamental and very important module in analog and mixed-signal integrated circuits. This paper has launched exhaustive analysis and study to every module of PLL and its key part (VCO) is also improved.The history of phase-locked technology and the actuality of research on it are introduced. And then beginning with the fundamental principles of a phase-locked system, we build the mathematical model based on the architecture of the traditional analog PLL, and afterwards investigate some of its characters such as tracking, acquisition, noising, and stability. The system parameters are developed at the same time, and some universal conclusions on the theoretical analysis of PLL are reached.Then, we have carried on analysis and research to the theory of differential delay ring voltage controlled oscillator ( VCO ). On this basis, a improved differential delay ring VCO with more efficient loads is described. This circuit has been designed and implemented in 0.35μm CMOS technology. Hspice simulation results of the circuit show that there is a good linear characteristic for control voltage versus frequency and a wide frequency range. Low phase noise and low power dissipation have been also observed. The circuit design is realized and works at a 2.5V low supply voltage. But its performance is as same as common PLL at a 5V voltage. So the PLL performance is better than other PLLs at a 5V voltage, especially in power consumption and frequency.Finally, the improved PLL circuit used in the frequency synthesizer is composed of the improved VCO, phase/frequency detector and charge pump. Hspice simulation results show that the PLL performance is better than other PLLs implemented by other VCO in the same CMOS technology.