Research And Design Of Low Power Charge Pump Phase Lock Loop For Clock Generation

Demand of modern measurement systems in submicron CMOS process introducednew challenges in design of low power high frequency clock generation systems.Technical possibilities for clock generation using classical crystal oscillator is limited totens of megahertz. Thus,1GHz and above clock generation is not possible without afrequency multiplier system, which put forward higher requirements for the phase-lockedloop design.This paper introduced the CPPLL at first, analyzed the basic principles of it. Thenestablished the linear mathematical model of the phase-locked loop in locked state, withwhich we analyzed its stability and response behavior under different parameters, thengave out the key performance indicators in the PLL. Starting with the basic principles andstructure, we studied the basic theory of every module in a CPPLL, did an indepth studyabout the implementation of the PFD, non-ideal effects of CP, the impact of LPF’s order.A systematic study about the most important part of the system: VCO, has been done. Weresearched several methods to reduce its phase noise. Based on the theory learned and agoal of high frequency low power clock, we designed a CPPLL with a frequency of1.1GHz. Combined with manual calculations and system stability analysis with Matlab,we proposed a transistor-level design on PFD, CP, LPF, VCO and DIVIDER, with aprocess of TSMC18rf. As for the PFD dead zone and speed, we achieved it by using asingle-phase clock flip-flop,with which the PFD have faster speed of work and no need toworry about the problem of the dead zone. CP has used the differential structure with anamplifier to clamp the electronic level. The cascode current source and other measures canimprove the non-ideal effects. VCO has used the LC-tank resonance with a cross couplingstructure to achieve negative resistance, using a large capacitance to filter the phase noiseon the tail current source. This paper designed and achieved a CPPLL with a1.1GHz center frequency, andhad good linearity within1to1.2GHz. The power consumption was reduced to2.709mW.The system can work steady at different corners. VCO has used a large capacitance tofilter the phase noise and achieved a3.5~4.5dBc/Hz’s improvement. VCO’s phase noisewas-107.8dBc/Hz at1MHz offset.