Design Of Frequency-locked Loop Circuit Based On Resistive Frequency To Voltage Convertion

The single-photon detection system based on the all-solid-state photodiode APD(Avalanche Photodiode)provides a highly sensitive detection of photons,which lays an important foundation for quantum communication technology.The GHz gated clock provides the dynamic bias signal required for the operation of the APD detector,which plays an important role in ensuring single-photon sensitive detection.Aiming at the specific requirements of single photon detection system in the background of quantum communication applications,a certain high frequency and sufficient high time is needed for the clock.A FLL clock generation circuit based on switched capacitor is designed.First,the frequency of the voltage-controlled oscillator output is converted into a resistor through a switched capacitor,and the reference current can be connected to complete the frequency-to-voltage conversion.The error voltage generated after comparison with the reference voltage is amplified by the error amplifier,and the voltage controlled oscillator is output,and then adjust oscillation frequency.In the frequency-to-voltage converter,the original charge sharing method is replaced by the switched capacitor technology,which accelerates the frequency conversion rate and reduces the FLL lock time.High-order closed-loop control system formed by FLL,the output clock has a good inhibitory effect on process and temperature drift.Secondly,the voltage controlled oscillator is reduced to the minimum two-stage delay ring structure,the modeling analysis of the corresponding VCO and frequency-to-voltage converter is completed,and the system model is optimized to maximize the bandwidth and reduce the output phase noise of the voltage-controlled oscillator,increase the FLL output frequency and reduce power consumption.Finally,under the premise of streamlining the area,the layout design focuses on suppressing the frequency drop caused by parasitic effects,improving the critical path matching degree,and ensuring the effective realization of design performance.This thesis is based on TSMC 0.35?m standard CMOS process and Cadence EDA tool to complete the construction,layout design,front and back simulation and streamline verification of FLL system.The test results show that the output frequency ranges from 0.75 GHz to 1.26 GHz under the condition of 3.3V power supply voltage and normal temperature 27°C.When the reference voltage is 1.45 V,the FLL can output a clock frequency of 1.039 GHz with a rising edge of 109 ps,a falling edge of 120 ps,a duty cycle of 53.42%,a rms jitter of 35.24 ps,a power consumption of 105.6mW,and a high-frequency clock signal.Suitable for GHz gating applications in single photon detection.