Research Of Frequency Synthesizer Using Ring Oscillator Applied To Wide-Band Data Communication

Almost all modern communication systems need stable periodic signals, clocks, to provide basic timing for functions. The generation of stable periodic signal has been an urgent issue to be resolved due to the fabrication process limitation. This thesis has systematically researched the PLL based frequency synthesizer from the aspects of primary theory, linearly modeling and loop-filter performance. Also two low-cost high-performance frequency synthesizers have been designed where ring oscillator is chosen as the core circuit considering the factors like feasibility of integration, small area and multiple phases.First of all, detailed reasoning procedure of input transient response for PLL 2-order linear model has been obtained to guide the selecting of loop damping factor, as well as analyze and validate the stability of 3-order open-loop and close-loop, indicating the difference and application range between 3-order open-loop parameters and direct close-loop ones. Meanwhile, the thesis has summarized several noise models for oscillator from the side of applicability, choosing Eken-amended DaiLiang model as noise estimation basis for ring oscillator behavior-level design and verifying by transistor-level simulation.Secondly, systematic summarization has been given on the available typical ring oscillator structure. The conflict between a small gain of Voltage Controlled Oscillator (VCO) and large frequency variation due to process and temperature fluctuation in high frequency application leads to the design of a new multi-pass cross-coupled delay cell with selectable loading controlled by automatic switches. This design has effectively resolved the issue that the gain curve of high frequency ring oscillator can not cover the centre frequency under extreme process corners.Then, in order to trade off between the cost and performance of super-fine phase when realizing the low-jitter low-power high-performance frequency synthesizer for Ethernet application, a novel dynamic voltage-mode phase interpolator with 8-stage differential ring VCO has been provided satisfying the requirement of transmitter and receiver simultaneously. The chip has been implemented in SMIC 0.18-um standard CMOS process and achieved an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power dissipation is smaller than 4mW from a 1.8V supply voltage.Finally, a high-frequency frequency synthesizer which adopts the new multiple-pass ring VCO with frequency calibration in different process corners has been desinged. The whole design flow includs behavior-level, circuit-level, layout, PCB and measurement. Besides the ring VCO, the loop uses differential Charge Pump (CP) and a novel Differential-To-Single (DTOS) module to convert differential output of CP to single one. The DTOS has a precise gain which adjusts equivalent VCO gain in loop. Meanwhile it can change the control voltage level to cater for VCO and produces an additional high-frequency pole for noise filtering. The chip was implemented in SMIC 0.18-um standard CMOS technology and core power supply is 1.8V. It achieves good phase noise and jitter performance (-100dBc/Hz@1MHz, carrier=5.4GHz) by using waveform generator as the reference clock.