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Design Of High-speed Clock Circuit For Single Photon Detection

Posted on:2021-10-16Degree:MasterType:Thesis
Country:ChinaCandidate:C LiuFull Text:PDF
GTID:2518306557989939Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The single photon detection system based on avalanche photodiode has broad application prospects in military,spectral measurement,bioluminescence,and optical fiber sensing.With the increasing demand for detection speed,gated quenching as a control method for single-photon detection,the frequency of the gated clock often determines the maximum rate of single-photon detection.Therefore,a gated clock with a frequency above 1 GHz plays a vital role in high-speed single-photon detection systems.In order to meet the requirements of single-photon detection on the gated clock,this paper designs a highfrequency clock circuit for single-photon detection based on the closed-loop frequency locked loop structure.The FLL system uses a reference clock as the input drive signal,and a programmable frequency divider changes the frequency division ratio to adjust the output frequency to achieve the frequency multiplication function of the input reference frequency.The frequency-to-voltage conversion circuit based on the switched capacitor resistance type uses a complementary structure,which can effectively reduce the ripple on the converted voltage and help reduce the output clock jitter.The voltage-controlled oscillator uses a two-stage fully differential delay cell to form a ring vibration structure,while increasing the output frequency,the power consumption is effectively reduced.The overall loop is designed and manufactured with 1.8V devices.In order to obtain an output swing of 5V,the output stage uses a level shift circuit to realize the swing of the output signal from 1.8V to 5V.Based on TSMC 0.18?m standard CMOS process,this paper completes circuit parameter and layout design,front and back simulation on Cadence platform.Measurement results indicate that the output frequency range is 0.65 GHz ? 1.16 GHz for the FLL.The clock duty cycle is 50.3%,the swing amplitude is 1.03 V,and the RMS jitter is 155.03 ps at the typical frequency of 977.3MHz,then the power consumption is 50.4m W.The output frequency can meet the requirements of the single photon detection gated clock,but the swing amplitude is too small to limit the application of this clock.For the problems that occurred during the test,the paper finally analyzed and explained in detail,and put forward a series of improvement measures.
Keywords/Search Tags:frequency-locked loop, voltage-controlled oscillator, frequency-voltage conversion, clock jitter, level-shift circuit
PDF Full Text Request
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