Design Of Low Jitter Multi-Phase Clocks Generation Circuit Applied To TDC

Along with the continuous expansion of the scale of the system on chip, and the shrinking of feature dimension, the operating frequency of the chip is higher and higher, high-frequency clock generation circuits that are implemented by ring oscillator have applied widely to the ultra high-speed system chips due to the advantages of on-chip integration, multi-phase and simple structure. But within the traditional two-segmented time-to-digital application, the clock frequency would directly limit the improvement of accuracy and resolution of TDC as respect to the manufacturing process, supply voltage and ambient temperature, as well as clock random jitters. Therefore multi-phase clock generations based on temperature compensation architecture have not been to meet fundamental demands of TDC counters.In order to enhance the stability of the frequency in this thesis architecture comparison and theoretical analysis are presented from the system perspective for the frequency-locked loop and phase-locked loop, and the principal of feedback system is elaborated. Besides the loop stability and phase noise models would be focused further, and the low phase noise design methods are also proposed. For the FLL system, the improved frequency-to-voltage converter is present based on the narrow pulse generation logic and charge-shared technology, and the output clock frequency will be sampled for achieving the voltage conversion process, then the comparison with the reference voltage at the input port of the error amplifier, finally the errors are used to adjust dynamically the output frequency, tracking with the frequency. For the PLL system, the charge pump based on the current feedback approach could effectively enhance the matching precision of current, and the dividers consisted of the true single phase clock DFFs have low power consumption and the anti-noise ability.Based on TSMC 0.35?m CMOS process, the designed circuits are simulated and verified with the Cadence platform. Measurement results indicate that for the FLL system, the inherent frequency bias is 7.4MHz approximately, and the RMS jitters of clock signals reach to 38ps at the typical frequency 180MHz. For the PLL system, when the oscillator frequency is 180.004MHz, and the duty ratio is 51.12%, then the phase deviations reach ±8.20%, the RMS jitters of clock signals are 4.23ps and the pk-pk jitters are 38.45ps. Take the above verification results and the specific application into consideration, the designed circuits could meet the basic needs of two-level TDC. Finally the existing problems during the measurement would be analyzed further, and the improvement of accuracy error and clock jitters will be suggested in the following working.