A Low-Power, Low-Phase Noise Voltage Controlled Oscillators For Ultra Low Voltage Application

The explosive growth in wireless communications has driven universities and companies to produce wireless transceivers at low-cost, low-power, and compact size, while the VCO is a critical device of wireless transceivers. It works as a local oscillator for frequency translation and channel selection in the transceivers but suffers phase noise.The line-width of CMOS technologies is projected to keep scaling deeper into nanoscale dimensions for the next two decades. This will increase the functionality density, the intrinsic speed of the devices and thus the signal processing capability of the circuits. However, in order to maintain reliability, to avoid breakdown, to avoid thermal problems and to reduce power density, the maximum supply voltage has to be scaled down appropriately. But the transistor's threshold voltage is not reduced as aggressively. The low power supply voltages and the relatively large device threshold voltages are an obstacle to high performance analog circuit design. At supply voltages below 1 V, the design of analog circuits becomes very challenging since the traditional circuit techniques do not have sufficient voltage headroom.This thesis aims at realizing a chip design of low phase noise, low power voltage-controlled oscillator integrated circuit for ultra low voltage (0.5V) application. At present, the VCO for ultra low voltage application on the international is still in its infancy. The corresponding products come out still need certain time. Research on the VCO in our country is prosperity over the past few years, but they often pay attentions on the normal supply voltage environment research, just following the footsteps of the oversea existed products. In the case that the CMOS process technology in our country can already come up to an international advanced level, so we can carry out great-leap-forward development through researching the topics at the international level. Thus, these is important significance to improving the overall competitiveness of integrated circuit industry of our country.The main contents and innovative points of this dissertation are list below.Firstly, it covers some general considerations like the physical analysis of the integrated inductor, the existing electrical models to model them, and some methods to improve the quality factor of an integrated inductor. And it also analyses the influence of the geometrical parameters in the inductor's performance and will establish the design guidelines for the definition of the elements geometrical characteristics. It also introduces some new techniques to improve the quality factor.Secondly, it describes the physical phenomena that takes place in the different types of variable capacitor structures currently available in standard integrated circuits fabrication processes. And it also introduces the electric and magnetic field distributions in the varactors. Based on physical dimensions and on the properties of the fabrication processes, the electrical models of varactors are derived. Some important design rules to consider when dealing with the optimization of the performance of an integrated varactor are summarized. It also analyses the influence of the geometrical parameters in the different types of varactors' performance.Thirdly, we have studied four analysis methods of phase noise: linear time invariant (Lesson's), linear time varying (Hajimiri's), nonlinear perturbation analysis (Demir's) and mechanistic physical model (Rael's). The underlying physics of LC oscillators is analyzed in detail. The general process of LC VCOs' design and optimization is summarized. Energy conservation and VCO phase noise theory applied to the tank design leads to the concept of systematic high inductance LC tank VCO design for low power low phase noise oscillator designs. We summarize many techniques of lowering phase noise. Using these techniques, the low phase noise low power consumption VCO can operate from a 0.5 V supply.Fourthly, for ultra low voltage applications, in aspect of circuit implementation, various structures of PFD, CP, divider are discussed respectively. In order to overcome dead zone of PFD and improve operating frequency of circuit, a modified precharge PFD (MPTPFD) is used and optimized. With the reduced supply voltage, a novel structure for a CP circuit, which a negative feedback is employed, is proposed to achieve perfect current matching in a large range of the output voltage. The Extended True Single-Phase-Clock (ETSPC), an extension of the TSPC CMOS circuit technique, is proposed and analyzed. A complete dual-modulus prescaler is implemented, and a 3 GHz rate is achieved with low power consumption.Finally, 3-T LC VCO is implemented in SMIC 0.13μm 1P8M CMOS process, and the CP PLL has already been taped out. Measurement results have shown that the 3-T LC VCO provide the phase noise of -119.8～-121.5 dBc/Hz at 1-MHz offset, and the range of the output frequency is about 2.1～2.3 GHz while dissipating 685μW from a 0.5 V supply. The FOM of the VCO is -188.7～-190.3 dB. This design has reached the leading level in China. Using the VCO as the key componet, an ultra low voltage, low power, low phase noise PLL is presented in this thesis and the chip is being taped out in SMIC.