High Performance X – Band Frequency Synthesizer

Channel is one of the most valuable resources in communication system. Since low frequency channels are occupies by more and more communication protocols, high frequency channel application is becoming a resolution for modern communication systems. As a physical understructure of communication systems, the development of radio frequency(RF) techniques also aims at higher frequency applications. High frequency communication systems require wide frequency range and high signal to noise ratio(SNR), which brings challenge to design of RF receivers and also its critical component – frequency synthesizer for high frequency applications.This thesis aims at satisfying the stringent requirement of frequency range, phase noise, and settling time for X-band(8-12GHz) frequency synthesizer applications. A series of innovative designs are proposed to improve synthesizer performance, and the following works are completed during circuit implementation:At first, phase locked loop(PLL) based frequency synthesizer suited for X-band application is adopted to satisfy the performance requirement of receivers which are used in high frequency communication systems. Performance specifications is made to the proposed frequency synthesizer and allocated to all building blocks, using the low noise down-converter(low noise block, LNB) for satellite broadcasting system as a design objective. Validity of system parameters is demonstrated through behavior level simulations.Second, in order to improve low power and low noise requirements of X-band frequency synthesizers, some 65 nm CMOS technology based circuit implementation methods are proposed during block design. A voltage controlled oscillator(VCO) phase noise optimization method based on frequency calibration, tuning voltage range extension and low noise bias voltage is proposed for wide band VCOs, which reduces out-of-band phase noise of the proposed frequency synthesizer. A low noise, high power supply rejection ratio current bias is proposed to improve phase noise performance of the proposed crystal oscillator(XO), which reduces in-band phase noise of the proposed frequency synthesizer.Third, a multi-phase clock sampling based automatic frequency calibration(AFC) acceleration algorithm is proposed to overcome the low speed disadvantage of conventional AFCs. Very fast AFC speed and high calibration accuracy is achieved. At the same time, the multi-mudulus frequency divider is proposed to be reused during calibration process, as a multi-phase generator. Divider function is fully used without adding new circuit and power dissipation.At last, a frequency synthesizer suitable for X-band communication system is implemented under 65 nm CMOS technology with 0.2mm2 core circuit area. Frequency range of the proposed frequency synthesizer covers 9GHz to 12 GHz and its phase noise is less than-37 dBc for all output frequency, integrated from 10 kHz to 13 MHz frequency offset, which is less than 0.8° calculated as phase error. Spot phase noise at 1MHz frequency offset is less than 110dBc/Hz. Total current consumption is less than 33 mA. AFC time is less than 1.44μs and the PLL settling time is less than 20μs. Advantages of the proposed techniques are demonstrated through the experimental result quoted above. Performance of proposed frequency synthesizer is comparable among international academic publications.