Design On Behavioral Model And Key Circuits Of 18-bit Pipeline ADC

As a hub connecting the analog domain and the digital domain,the analog-to-digital converters(ADC)are widely used in instrumentation,wireless communication and other electronic information systems.With the continuous development of semiconductor manufacturing process and integrated circuit design technology,electronic information systems require ADCs with high resolution and speed.Therefore,the pipeline ADC with high speed and high resolution has become a research hotspot.In this dissertation,the behavioural model of the 18-bit pipeline ADC is studied and designed in detail,and the design of key circuits is completed for the requirements of ADC resolution and speed in the field of high-end instrumentation.Aiming at the poor linearity of the traditional redundant 0.5-bit calibration algorithm,a redundant 1-bit calibration algorithm with an overflow flag is used.By adding two comparators,the algorithm makes the residual signal output by the operational amplifier all in the same range,which improves the linearity;By analyzing two multiplying digital-to-analog converter(MDAC)structures of charge redistribution and capacitance flip-around,a hybrid structure MDAC circuit is adopted.It achieves a large amplification while reducing the operational amplifier bandwidth and noise;Through a comprehensive analysis of circuit noise,comparator offset voltage and operational amplifier output swing,the resolution of each pipeline stage is determined.Based on the above analysis and design,a top-level architecture of the 18-bit pipeline ADC is determined.After that,the 18-bit pipeline ADC is modeled in detail by using Verilog-A language.The behavioral model verifies the founction of the top-level architecture.Moreover,the effects of comparator offset,limited gain of operational amplifier and capacitance mismatch on the overall ADC system are studied with the correctness of the corresponding digital algorithm.Since the resolution of each pipeline stage is high and the FLASH stage is a two-stage structure,in order to meet the resolution and timing requirements of different pipeline stages,two kinds of comparators with high precision pre-amplification latch structure are designed by adopting the input offset storage technology.In order to adapt to the front-end sampling network of sample-and-hold amplifier-Less(SHA-less)and the input signal with large swing,a bootstrap switch circuit with dynamic switching of switch substrates is proposed by improving the traditional bootstrap switch circuit.In addition,the high gain and high swing operational amplifier of the two-stage structure is designed to meet the output precision and output swing requirements of the first pipeline stage.The first stage is a sleeve-type cascode structure,which provides high gain for the circuit,and the second stage is a simple differential structure,which further improves the gain of the overall circuit and obtains a large output swing.The schematic diagram and layout design of the key sub-circuits of the 18-bit pipeline ADC are implemented in a 0.18μm CMOS process,and the overall layout area is 4.7×2.4 mm~2.The post-simulation results show that the 18-bit pipeline ADC has good dynamic performance in the entire Nyquist frequency range.