Design Of A 10bit 500MS/s Pipeline-SAR ADC

As a key circuit in modern communication system,the performance of analog-to-digital converter(ADC)directly determines the overall performance of communication system.Pipeline-SAR ADC(Pipeline-SAR ADC)is widely used in applications requiring medium-resolution and high-speed ADC,such as 802.11 ac wireless communication protocol,because of its high-speed and low-power feature,and well-adapted in advanced CMOS technology.Aiming at the application of modern high-speed communication system,a 10 bit 500MS/s low-power Pipeline-SAR ADC is designed in this thesis.The Pipeline-SAR ADC designed in this thesis is a two-stage structure.Both of the two SAR ADCs are 6bit.The inter-stage amplifier provides a gain of 4 and sets up 2 bit inter-stage redundancy..In first stage SAR ADC,this thesis proposes a Loop-unrolled structure based on self-switch-off comparator.After each comparison is completed,the current comparator is switched off by self-switch-off signal,which greatly reduces the power consumption of the Loop-unrolled structure without affecting the data latch of the comparator.At the same time,to reduce the mismatch between multiple comparators in Loop-unrolled structure,a background offset mismatch calibration method based on reference comparator is adopted.The introduction of reference comparator makes the background calibration to be completed without additional calibration cycle,thus ensuring the high-speed characteristics of the system.A gain-stable dynamic amplifier is used as the inter-stage amplifier.The gain of the dynamic amplifier is constructed as a proportional product of the same parameters to achieve gain stability,and its time sequence is optimized to avoid the introduction of additional clock phase.The second stage SAR ADC also pays attention to high-speed design which adopts alternative comparator structure,and uses foreground offset calibration for the two comparators to avoid introducing additional calibration cycle.Because the inter-stage amplifier only provides 4 times gain which leads to the small quantization range of the second stage,non-binary scaled redundancy is used in the design of the second stage CDAC to reduce the influence of DAC settling error.In order to ensure the integrity of the whole Pipeline-SAR ADC design,the digital code combination circuit and the global clock generation circuit are also designed.The presented Pipeline-SAR ADC is implemented in the TSMC 40 nm CMOS process.Post-simulation shows the ADC exhibits a 9.2ENOB,64.5dB SFDR and 7.52 mW power consumption at a Nyquist input frequency at tt-corner when operating at a sampling rate of 500MS/s and 1.1V power supply.FoM is 25.76fJ/conv.step,and meets the design requirements.