A 14Bit 500MSPS Dual Channel Time Interleaving Research On Key Technologies Of Pipelined ADC

With the constant reduction of integrated circuit process nodes,the requirements for analog circuit design have become increasingly higher.As a result of various factors at home and abroad,the development of high-speed and high-precision analog-to-digital converter(ADC)chips has become increasingly important.The pipelined ADC architecture has become the preferred architecture for high-speed and high-precision ADCs because it can well balance speed and accuracy.This thesis is based on the 0.18μm Si Ge Bi CMOS process and focuses on researching the key technologies of a 14 Bit 500 MSPS dual-channel interleaved pipeline ADC.A detailed comparative analysis of the technical solutions and core circuits of each module of the circuit is conducted,and a behavioral-level model of the entire ADC is built using Simulink to simulate and verify the theoretical design.The overall circuit adopts a multi-stage pipeline architecture of 4+3.5+3+2.5+3+3,with the input signal first entering the multi-stage pipeline structure through an Input Buffer circuit,followed by each stage of the pipeline performing data conversion on the input voltage to obtain the final quantization result.In the ADC circuit design,this thesis uses the"replica current technology"source follower as the input buffer circuit,which provides an input signal that meets the linearity and driving capability requirements for the later stages.The pre-amplifier and latch technique is used to achieve high-speed and low-error comparator circuit outputs for the sub-ADC,which reduces the impact of comparator kickback noise and offset voltage on the comparator output results.Based on the Bi CMOS process,a two-stage nested amplifier circuit is used to achieve the high gain and high bandwidth requirements of the operational amplifier circuit,meeting the design requirements of the MDAC circuit.By sharing one operational amplifier between channels and satisfying the design specifications,the number of operational amplifiers used is reduced.A first-order compensation circuit is used to design a gap reference voltage of around 1.2 V that is independent of temperature and process.The total chip area is 2.414×1.512 mm~2,and the overall power consumption of the circuit is measured at 1.0245 W during DC simulation.A sinusoidal signal with a frequency of 7.5 MHz and a full swing of 1.8 V was used for the pre-simulation and post-simulation of the entire circuit under three temperature conditions in the TT process.Under normal temperature,the pre-simulation results were ENOB 13.71 Bit,SNR 84.31 d B,SFDR 99.4 d Bc.The post-simulation results were ENOB 12.23 Bit,SNR 75.69 d B,SFDR 86.72 d Bc.Compared with the pre-simulation,the post-simulation index has decreased to a certain extent.This is because in high-speed sampling situations,parasitic capacitance and resistance in the layout will slow down the establishment of the operational amplifier and reduce the overall gain.Channel mismatch and capacitor mismatch will also have a significant impact on the accuracy of conversion and the size of harmonics.Overall,two effective bits were lost and SFDR was reduced by 10 dBc.